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5331 条记录 (耗时 0.031 秒)

    MEMORY DEVICE AND SCHEDULING METHOD THEREOF
    41.
    发明公开
    MEMORY DEVICE AND SCHEDULING METHOD THEREOF 审中-公开

    公开(公告)号：US20240201858A1

    公开(公告)日：2024-06-20

    申请号：US18322798

    申请日：2023-05-24

    申请人： Samsung Electronics Co., Ltd.

    发明人： Nayeon Kim ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Jinin So ,  Kyoungwan Woo

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

    摘要： A memory includes: a request register configured to receive a first signal including a requester identifier using a first protocol from a host and configured to output a first priority corresponding to the requester identifier; a checker module configured to receive a second signal including a command and a request type from the host and using a second protocol that is different than the first protocol, where the checker module is configured to receive the first priority from the request register, and where the checker module is configured to determine a second priority of the command based on the first priority and the request type; a command generator configured to generate an internal command for memory operation based on the command; and a memory controller configured to schedule the internal command in a command queue based on the second priority.

    DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT
    42.
    发明公开
    DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT 审中-公开

    公开(公告)号：US20240201857A1

    公开(公告)日：2024-06-20

    申请号：US18168573

    申请日：2023-02-14

    申请人： Phison Electronics Corp.

    发明人： Po-Cheng Su ,  Yu-Cheng Hsu ,  Wei Lin

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

    摘要： A decoding method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending at least one read command sequence instructing to read a first physical unit in a rewritable non-volatile memory module; receiving response data from the rewritable non-volatile memory module, wherein the response data includes a plurality of identification bits, and the plurality of identification bits reflect a voltage variation of a first bit line where a first memory cell in the first physical unit is located during a discharge process; determining a decoding parameter corresponding to the first memory cell according to the plurality of identification bits; and decoding data read from the first memory cell according to the decoding parameter.

    METHOD OF MANAGING INDEPENDENT WORD LINE READ OPERATION IN FLASH MEMORY AND RELATED MEMORY CONTROLLER AND STORAGE DEVICE
    43.
    发明公开
    METHOD OF MANAGING INDEPENDENT WORD LINE READ OPERATION IN FLASH MEMORY AND RELATED MEMORY CONTROLLER AND STORAGE DEVICE 审中-公开

    公开(公告)号：US20240192856A1

    公开(公告)日：2024-06-13

    申请号：US18078077

    申请日：2022-12-08

    申请人： Silicon Motion, Inc.

    发明人： Tzu-Yi Yang

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

    摘要： A method of managing operation commands for a flash memory includes: providing a first command queue for receiving and storing a plurality of normal operation commands; providing at least one word line read (IWLR) command queue for receiving and storing a plurality of IWLR operation commands; issuing a lock state command between each two consecutive IWLR operation commands to the at least one second command queue; determining a selected command queue from the first command queue and the at least one IWLR command queues according to the lock state command; and delivering an operation command from the selected command queue to the flash memory.

    Random write method and apparatus
    44.
    发明授权
    Random write method and apparatus 有权

    公开(公告)号：US12008240B2

    公开(公告)日：2024-06-11

    申请号：US17925687

    申请日：2021-01-23

    申请人： INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.

    发明人： Qi Song ,  Baolin Zhao

    IPC分类号： G06F3/06 ,  G06F12/02 ,  G06N3/0442

    CPC分类号： G06F3/0613 ,  G06F3/0653 ,  G06F3/0679 ,  G06F12/0246 ,  G06N3/0442 ,  G06F2212/7211

    摘要： A random write method includes: using a wear-leveling module to scan the number of free blocks and the number of bad blocks in a target super logic unit; using a lookup management module to iteratively update, according to the number of current remaining solid-state disk data frames, the number of historically weighted solid-state disk data frames in a long short-term memory network manner; using dynamic write arbitration to determine an adjustment stage based on the number of historically weighted solid-state disk data frames, and determining the expected number of read and write operations per second based on the adjustment stage; and re-updating the number of historically weighted solid-state disk data frames, and adjusting the actual number of read and write operations per second based on the re-updated number of historically weighted solid-state disk data frames and the expected number of read and write operations per second.

    OPERATING METHOD FOR A MEMORY, A MEMORY, AND A MEMORY SYSTEM
    46.
    发明公开
    OPERATING METHOD FOR A MEMORY, A MEMORY, AND A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240168642A1

    公开(公告)日：2024-05-23

    申请号：US18148763

    申请日：2022-12-30

    申请人： Yangtze Memory Technologies Co., Ltd.

    发明人： Weijun Wan

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0613 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

    摘要： An operating method for a memory, a memory, and a memory system are provided in the present application. The memory includes at least a plurality of word lines and a plurality of strings, and the plurality of word lines include a target word line, and each word line is coupled to a plurality of strings. Each string includes a plurality of memory cells. In accordance with the operating method provided by the present application, the first verification and the second verification are performed on a plurality of target memory cells with first and second verify voltages during performing a first programming operation on a plurality of target memory cells in target string coupled to the target word line, and the second start program voltage is determined based on at least the second verification result, ensuring the accuracy of the second start program voltage.

    DATA STORAGE METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT
    47.
    发明公开
    DATA STORAGE METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT 审中-公开

    公开(公告)号：US20240168641A1

    公开(公告)日：2024-05-23

    申请号：US18088604

    申请日：2022-12-25

    申请人： PHISON ELECTRONICS CORP.

    发明人： Chih-Kang Yeh

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

    摘要： A data storage method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving at least one write command instructing to store target data from a host system; encoding the target data to generate parity data; and respectively storing the target data and the parity data in a first physical management unit and a second physical management unit, and each of the first physical management unit and the second physical management unit crosses multiple chip enabled (CE) regions. In addition, in the first physical management unit, first data is stored in a first chip enabled region among the chip enabled regions. In the second physical management unit, first parity data for protecting the first data is stored in a second chip enabled region among the chip enabled regions, and the first chip enabled region is different from the second chip enabled region.

    Memory system controlling nonvolatile memory
    48.
    发明授权
    Memory system controlling nonvolatile memory 有权

    公开(公告)号：US11983412B2

    公开(公告)日：2024-05-14

    申请号：US17585845

    申请日：2022-01-27

    申请人： Kioxia Corporation

    发明人： Shuichi Watanabe

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0613 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

    摘要： According to one embodiment, a controller of a memory system calculates an amount of transferred data per unit time in response to completion of processing of a first I/O command. While the calculated amount of transferred data per unit time exceeds a first threshold, the controller does not transmit, to a host, a completion response indicating completion of the first I/O command. When the calculated amount of transferred data per unit time is equal to or less than the first threshold, the controller transmits, to the host, the completion response indicating the completion of the first I/O command.

    APPARATUS AND METHOD FOR DYNAMICALLY RECONFIGURING MEMORY REGION OF MEMORY DEVICE
    49.
    发明公开
    APPARATUS AND METHOD FOR DYNAMICALLY RECONFIGURING MEMORY REGION OF MEMORY DEVICE 审中-公开

    公开(公告)号：US20240152278A1

    公开(公告)日：2024-05-09

    申请号：US18327323

    申请日：2023-06-01

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Maksim Ostapenko ,  YOUNGSAM SHIN

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0613 ,  G06F3/0631 ,  G06F3/0673 ,  G06F3/0656

    摘要： An electronic device comprises a host processor comprising a memory controller connected to a memory device comprising a near memory processing unit. The host processor is configured to detect a system memory shortage for an operation of an operating system (OS), configure a memory region of the memory device for use in a memory pool of the OS in response to the system memory shortage, identify a request to execute an acceleration logic, and configure the memory region of the memory device for direct access by the near memory processing unit in response to the request to execute the acceleration logic.

    Host rate adjustment using free space values
    50.
    发明授权
    Host rate adjustment using free space values 有权

    公开(公告)号：US11977736B2

    公开(公告)日：2024-05-07

    申请号：US17961050

    申请日：2022-10-06

    申请人： Micron Technology, Inc.

    发明人： Donghua Zhou

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0608 ,  G06F3/0613 ,  G06F3/0634 ,  G06F3/0653 ,  G06F3/0679

    摘要： Methods, systems, and apparatuses include receiving a current free space value and a historic delta value. A delta value is calculated using the current free space value, a target free space value, and the historic delta value. A delta region is determined using the delta value. A new host rate is calculated using the determined delta region, the calculated delta value, and the historic delta value. The new host rate is sent to a host device causing the host device to change a current host rate to the new host rate.