公开(公告)号：US20100053822A1

公开(公告)日：2010-03-04

申请号：US12200034

申请日：2008-08-28

申请人： Haiwen Xi ,  Paul Anderson ,  Zheng Gao ,  Xiaobin Wang ,  Dimitar V. Dimitrov ,  Song S. Xue

发明人： Haiwen Xi ,  Paul Anderson ,  Zheng Gao ,  Xiaobin Wang ,  Dimitar V. Dimitrov ,  Song S. Xue

IPC分类号： G11B5/127

CPC分类号： G01R33/093 ,  B82Y25/00 ,  G11C11/155 ,  G11C11/161 ,  G11C11/1675

摘要： A magnetic tunnel junction cell that has a ferromagnetic pinned layer, a ferromagnetic free layer, and a non-magnetic barrier layer therebetween. The free layer has a larger area than the pinned layer, in some embodiments at least twice the size of the pinned layer, in some embodiments at least three times the size of the pinned layer, and in yet other embodiments at least four times the size of the pinned layer. The pinned layer is offset from the center of the free layer. The free layer has a changeable vortex magnetization, changeable between clockwise and counterclockwise directions.

摘要翻译： 磁性隧道结电池，其具有铁磁性钉扎层，铁磁性自由层和它们之间的非磁性阻挡层。 自由层具有比被钉扎层更大的面积，在一些实施例中为钉扎层的尺寸的至少两倍，在一些实施例中为被钉扎层的尺寸的至少三倍，并且在其它实施例中为至少四倍的尺寸 被钉扎层。 固定层从自由层的中心偏移。 自由层具有可变的涡流磁化，可在顺时针和逆时针方向之间改变。

公开(公告)号：US20090065855A1

公开(公告)日：2009-03-12

申请号：US12005146

申请日：2007-12-21

申请人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

发明人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L29/66484 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor device is formed on a semiconductor substrate. The device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface and a body bottom surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and at least part of the body into the drain, wherein the active region contact trench is shallower than the body bottom surface, and an active region contact electrode disposed within the active region contact trench.

摘要翻译： 半导体器件形成在半导体衬底上。 该器件包括漏极，覆盖漏极的外延层和有源区。 有源区域包括设置在外延层中的主体，具有主体顶表面和主体底表面，嵌入在主体中的源，从主体顶表面延伸到主体中，延伸到外延层中的栅沟槽， 设置在所述栅极沟槽中的栅极，延伸穿过所述源极和所述主体的至少一部分进入所述漏极的有源区接触沟槽，其中所述有源区接触沟槽比所述主体底表面浅，以及设置在所述栅极沟槽内的有源区接触电极 有源区接触沟槽。

公开(公告)号：US20090065814A1

公开(公告)日：2009-03-12

申请号：US12005166

申请日：2007-12-21

申请人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

发明人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

IPC分类号： H01L29/78 ,  H01L21/338

CPC分类号： H01L29/7811 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/8725

摘要： A semiconductor device is formed on a semiconductor substrate. The semiconductor device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and the body into the drain, an active region contact electrode disposed within the active region contact trench, wherein the active region contact electrode and the drain form a Schottky diode, and a Schottky barrier controlling layer disposed in the epitaxial layer adjacent to the active region contact trench.

摘要翻译： 半导体器件形成在半导体衬底上。 半导体器件包括漏极，覆盖漏极的外延层和有源区。 有源区域包括设置在外延层中的主体，具有主体顶表面，嵌入在主体中的源，从主体顶表面延伸到主体中，延伸到外延层中的栅沟槽，设置在栅极中的栅极 沟槽，延伸穿过源极和本体进入漏极的有源区接触沟槽，设置在有源区接触沟槽内的有源区接触电极，其中有源区接触电极和漏极形成肖特基二极管，以及肖特基势垒控制 层，设置在与有源区接触沟槽相邻的外延层中。

公开(公告)号：US20060252866A1

公开(公告)日：2006-11-09

申请号：US11120789

申请日：2005-05-03

申请人： Xiaobin Wang ,  Daniel Doe ,  Patricia Savory ,  Kenneth Lambert

发明人： Xiaobin Wang ,  Daniel Doe ,  Patricia Savory ,  Kenneth Lambert

IPC分类号： C08K5/05

CPC分类号： C09J4/00

摘要： Adhesive formulations having acrylate monomer or methacrylate monomer, or mixtures thereof, and having a reducing agent and an initiator (e.g., peroxide). The formulations may include a chelating agent solution to improve storage stability and other properties. Further, the mole ratio of the initiator to the reducing agent may be adjusted to control weight loss of the adhesives during cure. Polyvinyl acetate or its derivatives may also be employed in the adhesive formulations to reduce weight loss during cure. Moreover, certain embodiments of the formulations include a toughening-agent copolymer having a glass transition temperature (of at least one domain) that is lower than −50° C. (−58° F.). These toughening-agent copolymers may be added to the adhesive formulations to improve impact strength and other properties of the cured adhesives at lower temperatures, e.g., −40° C. (−40 ° F.), while maintaining performance of the cured adhesives at higher temperatures, e.g., 82° C. (180° F.).

摘要翻译： 具有丙烯酸酯单体或甲基丙烯酸酯单体或其混合物并具有还原剂和引发剂（例如过氧化物）的粘合剂制剂。 制剂可以包括螯合剂溶液以改善储存稳定性和其它性质。 此外，可以调节引发剂与还原剂的摩尔比，以控制固化期间粘合剂的重量损失。 聚乙酸乙烯酯或其衍生物也可用于粘合剂制剂中以减少固化过程中的体重减轻。 此外，制剂的某些实施方案包括具有低于-50℃（-58°F）的玻璃化转变温度（至少一个结构域）的增韧剂共聚物。 这些增韧剂共聚物可以添加到粘合剂配方中，以在较低的温度例如-40℃（-40°F）下改善固化的粘合剂的冲击强度和其它性能，同时保持固化的粘合剂的性能 较高的温度，例如82°C（180°F）。

公开(公告)号：US20160315053A1

公开(公告)日：2016-10-27

申请号：US14242851

申请日：2014-04-01

申请人： Ji Pan ,  Daniel Ng ,  Anup Bhalla ,  Xiaobin Wang

发明人： Ji Pan ,  Daniel Ng ,  Anup Bhalla ,  Xiaobin Wang

IPC分类号： H01L23/552 ,  H02M1/44 ,  H01L29/66 ,  H02M3/158 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L23/552 ,  H01L29/0638 ,  H01L29/401 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66704 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7825 ,  H02M1/44 ,  H02M3/158

摘要： A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

公开(公告)号：US20150221734A1

公开(公告)日：2015-08-06

申请号：US14171777

申请日：2014-02-04

申请人： Yeeheng Lee ,  Xiaobin Wang

发明人： Yeeheng Lee ,  Xiaobin Wang

IPC分类号： H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L21/321 ,  H01L21/28 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L29/49 ,  H01L29/66

摘要： Semiconductor device fabrication method and devices are disclosed. The semiconductor power device is formed on a semiconductor substrate having a plurality of trench transistor cells each having a trench gate. Each of the trench gates having a thicker bottom oxide (TBO) formed by a REOX process on a polysilicon layer deposited on a bottom surface of the trenches.

摘要翻译： 公开了半导体器件制造方法和器件。 半导体功率器件形成在具有各自具有沟槽栅极的多个沟槽晶体管单元的半导体衬底上。 每个沟槽栅极具有较厚的底部氧化物（TBO），其通过REOX工艺在沉积在沟槽的底表面上的多晶硅层上形成。

公开(公告)号：US09030864B2

公开(公告)日：2015-05-12

申请号：US13611230

申请日：2012-09-12

申请人： Yuankai Zheng ,  Dimitar V. Dimitrov ,  Wei Tian ,  Dexin Wang ,  Zheng Gao ,  Xiaobin Wang

发明人： Yuankai Zheng ,  Dimitar V. Dimitrov ,  Wei Tian ,  Dexin Wang ,  Zheng Gao ,  Xiaobin Wang

IPC分类号： G11C11/16

CPC分类号： G11C11/161

摘要： Magnetic tunnel junctions having a specular insulative spacer are disclosed. The magnetic tunnel junction includes a free magnetic layer, a reference magnetic layer, an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the reference magnetic layer, and an electrically insulating and electronically reflective layer positioned to reflect at least a portion of electrons back into the free magnetic layer.

摘要翻译： 公开了具有镜面绝缘间隔物的磁隧道结。 磁性隧道结包括自由磁性层，参考磁性层，将自由磁性层与参考磁性层分离的电绝缘和非磁性隧道势垒层，以及电绝缘和电子反射层，其被定位成反射至少一个 部分电子返回自由磁性层。

公开(公告)号：US20140167212A1

公开(公告)日：2014-06-19

申请号：US13712980

申请日：2012-12-13

申请人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

发明人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

IPC分类号： H01L21/762 ,  H01L29/06

CPC分类号： H01L29/407 ,  H01L21/76205 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

摘要翻译： 公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。 在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到 星展集团

公开(公告)号：US08697520B2

公开(公告)日：2014-04-15

申请号：US13411422

申请日：2012-03-02

申请人： Yeeheng Lee ,  Yongping Ding ,  Xiaobin Wang

发明人： Yeeheng Lee ,  Yongping Ding ,  Xiaobin Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/7811 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.

摘要翻译： 具有多个晶体管的半导体器件包括具有非对称栅极的晶体管的端接区域。

公开(公告)号：US08553454B2

公开(公告)日：2013-10-08

申请号：US13400515

申请日：2012-02-20

申请人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  Dimitar V. Dimitrov ,  Alan Xuguang Wang ,  Xiaobin Wang

发明人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  Dimitar V. Dimitrov ,  Alan Xuguang Wang ,  Xiaobin Wang

IPC分类号： G11C11/14 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C11/1675 ,  G11C11/1659

摘要： Method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell. In accordance with some embodiments, a semiconductor memory has an array of non-volatile memory cells, and a control circuit which stores a first write command from a host to write data to said array. A write circuit flows a write current through an unconditioned first selected cell having a first block address associated with the first write command to write the first selected cell to a selected data state, and concurrently passes a thermal preconditioning current through a second selected cell having a second block address associated with the first block address. The write circuit further passes a thermal preconditioning current through a third selected cell having a third block address associated with the second block address in response to receipt by the control circuit of a second write command from the host associated with the second block address.

摘要翻译： 使用热预处理将数据写入非易失性存储单元的方法和装置。 根据一些实施例，半导体存储器具有非易失性存储器单元的阵列，以及存储来自主机的第一写命令以将数据写入所述阵列的控制电路。 写入电路通过具有与第一写入命令相关联的第一块地址的无条件的第一选定单元流动写入电流，以将第一选定单元写入所选择的数据状态，并且同时通过热预处理电流通过具有 与第一块地址相关联的第二块地址。 响应于控制电路接收到与第二块地址相关联的主机的第二写入命令，写入电路进一步传递热预处理电流通过具有与第二块地址相关联的第三块地址的第三选定单元。