Asymmetric Write Current Compensation
    2.
    发明申请
    Asymmetric Write Current Compensation 有权
    非对称写电流补偿

    公开(公告)号:US20110134688A1

    公开(公告)日:2011-06-09

    申请号:US13016445

    申请日:2011-01-28

    CPC classification number: G11C11/16 G11C11/1659 G11C11/1675

    Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.

    Abstract translation: 一种用于补偿非易失性单元中不对称写入电流的装置和方法。 单位单元包括开关装置和非对称电阻感测元件(RSE),诸如非对称电阻随机存取存储器(RRAM)元件或非对称自旋转矩传递随机存取存储器(STRAM)元件。 RSE相对于开关装置在物理上定位在单位单元内,使得用于编程RSE的硬方向与单元单元的简单编程方向对齐,并且用于编程RSE的简单方向与硬方向对齐 编程单元格

    FAULT-TOLERANT NON-VOLATILE BUDDY MEMORY STRUCTURE
    9.
    发明申请
    FAULT-TOLERANT NON-VOLATILE BUDDY MEMORY STRUCTURE 审中-公开
    故障的非易失性存储结构

    公开(公告)号:US20100037102A1

    公开(公告)日:2010-02-11

    申请号:US12269535

    申请日:2008-11-12

    CPC classification number: G11C29/846

    Abstract: Various embodiments of the present invention are generally directed to an apparatus and method for providing a fault-tolerant non-volatile buddy memory structure, such as a buddy cache structure for a controller in a data storage device. A semiconductor memory array of blocks of non-volatile resistive sense memory (RSM) cells is arranged to form a buddy memory structure comprising a first set of blocks in a first location of the array and a second set of blocks in a second location of the array configured to redundantly mirror the first set of blocks. A read circuit decodes a fault map which identifies a defect in a selected one of the first and second sets of blocks and concurrently outputs data stored in the remaining one of the first and second sets of blocks responsive to a data read operation upon said buddy memory structure.

    Abstract translation: 本发明的各种实施例通常涉及用于提供容错非易失性伙伴存储器结构的装置和方法,例如用于数据存储设备中的控制器的伙伴高速缓存结构。 布置非易失性电阻式感测存储器(RSM)单元块的半导体存储器阵列以形成伙伴存储器结构,其包括阵列的第一位置中的第一组块和位于阵列的第二位置的第二组块 阵列被配置为冗余地镜像第一组块。 读取电路解码故障映射,其识别所述第一和第二组块中的所选择的一个中的缺陷,并响应于所述好友存储器上的数据读取操作,同时输出存储在第一组和第二组中的剩余块中的数据 结构体。

    Asymmetric write current compensation
    10.
    发明授权
    Asymmetric write current compensation 有权
    不对称写入电流补偿

    公开(公告)号:US08320169B2

    公开(公告)日:2012-11-27

    申请号:US13333598

    申请日:2011-12-21

    CPC classification number: G11C11/16 G11C11/1659 G11C11/1675

    Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.

    Abstract translation: 一种用于补偿非易失性单元中不对称写入电流的装置和方法。 单位单元包括开关装置和非对称电阻感测元件(RSE),诸如非对称电阻随机存取存储器(RRAM)元件或非对称自旋转矩传递随机存取存储器(STRAM)元件。 RSE相对于开关装置在物理上定位在单位单元内,使得用于编程RSE的硬方向与单元单元的简单编程方向对齐,并且用于编程RSE的简单方向与硬方向对齐 编程单元格

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