公开(公告)号：US20100177460A1

公开(公告)日：2010-07-15

申请号：US12726467

申请日：2010-03-18

申请人： Keith R. Brenneman ,  Chris Wayne ,  Chris Stolarski ,  John T. Kinard ,  Alethia Melody ,  Gregory J. Dunn ,  Remy J. Chelini ,  Robert T. Croswell

发明人： Keith R. Brenneman ,  Chris Wayne ,  Chris Stolarski ,  John T. Kinard ,  Alethia Melody ,  Gregory J. Dunn ,  Remy J. Chelini ,  Robert T. Croswell

IPC分类号： H01G4/008 ,  H01G4/00

CPC分类号： H01G9/15 ,  H01G9/0029

摘要： An improved method for forming a capacitor. The method includes: providing a carrier with a channel therein; providing a metal foil with a valve metal with a first dielectric on a first face of the metal foil; securing the metal foil into the channel with the first dielectric away from a channel floor; inserting an insulative material between the metal foil and each side wall of the channel; forming a cathode layer on the first dielectric between the insulative material; forming a conductive layer on the cathode layer and in electrical contact with the carrier; lap cutting the carrier parallel to the metal foil such that the valve metal is exposed; and dice cutting to form singulated capacitors.

摘要翻译： 一种形成电容器的改进方法。 该方法包括：在其中提供具有通道的载体; 在所述金属箔的第一面上提供具有第一电介质的阀金属的金属箔; 将金属箔固定到通道中，使第一电介质远离通道底板; 在金属箔和通道的每个侧壁之间插入绝缘材料; 在绝缘材料之间的第一电介质上形成阴极层; 在阴极层上形成导电层并与载体电接触; 搭载平行于金属箔的载体，使得阀金属暴露; 和骰子切割以形成单个电容器。

公开(公告)号：US20080244885A1

公开(公告)日：2008-10-09

申请号：US11697477

申请日：2007-04-06

申请人： Gregory J. Dunn ,  Jovica Savic ,  Philip M. Lessner ,  Albert K. Harrington

发明人： Gregory J. Dunn ,  Jovica Savic ,  Philip M. Lessner ,  Albert K. Harrington

IPC分类号： H01G7/00

CPC分类号： H05K1/162 ,  H01G4/008 ,  H01G4/33 ,  H05K3/382 ,  H05K3/429 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2203/0315 ,  H05K2203/1536 ,  Y10T29/43

摘要： High capacitance value capacitors are formed using bimetal foils of an aluminum layer attached to a copper layer. The copper side of a bimetallic copper/aluminum foil or a monometallic aluminum foil is temporarily protected using aluminum or other materials, to form a sandwich. The exposed aluminum is treated to increase the surface area of the aluminum by at least one order of magnitude, while not attacking any portion of the protected metal. When the sandwich is separated, the treated bimetal foil is formed into a capacitor, where the copper layer is one electrode of the capacitor and the treated aluminum layer is in intimate contact with a dielectric layer of the capacitor.

摘要翻译： 使用连接到铜层的铝层的双金属箔形成高电容值电容器。 双金属铜/铝箔或单金属铝箔的铜面用铝或其他材料暂时保护，形成三明治。 处理暴露的铝以将铝的表面积增加至少一个数量级，同时不侵蚀受保护金属的任何部分。 当三明治分离时，处理的双金属箔形成电容器，其中铜层是电容器的一个电极，并且经处理的铝层与电容器的电介质层紧密接触。

公开(公告)号：US07427562B2

公开(公告)日：2008-09-23

申请号：US11557690

申请日：2006-11-08

申请人： Jaroslaw A. Magera ,  Gregory J. Dunn ,  Kathy D. Leganski

发明人： Jaroslaw A. Magera ,  Gregory J. Dunn ,  Kathy D. Leganski

IPC分类号： H01L21/4763

CPC分类号： H05K3/427 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/097 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49165

摘要： A method for forming closed vias in a multilayer printed circuit board. A dielectric layer is laminated to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture faces the other dielectric layer. Resin from one dielectric layer fills the cavities of approximately one half of the closed vias, and resin from the other dielectric layer fills the circular cavities of the remainder of the closed vias. The total amount of resin migrated from each of the dielectric layers into the closed via cavities is approximately equal.

摘要翻译： 一种在多层印刷电路板中形成封闭通孔的方法。 电介质层被层叠在每侧具有金属层的中心芯的一侧。 第二电介质层被层压到中心芯的另一侧。 已经通过部分地穿过但不完全穿透中心芯而形成中心芯上的闭合的通孔，然后通过直径小得多的孔从相对侧完成通孔，以形成完全穿透中心芯的通路 从一边到另一边。 然后通孔用金属电镀以基本上闭合较小的孔。 闭合通孔的大约一半被定位成使得闭合孔面对一个电介质层，并且其余的封闭通孔被定位成使得闭合孔面对另一介电层。 来自一个介电层的树脂填充了大约一半的封闭通孔的空腔，而另一个介电层的树脂填充了其余的封闭通孔的圆形空腔。 从每个介电层迁移到封闭通孔中的树脂的总量近似相等。

公开(公告)号：US07423608B2

公开(公告)日：2008-09-09

申请号：US11312286

申请日：2005-12-20

申请人： Gregory J. Dunn ,  Robert T. Croswell ,  George H. Kumpf ,  John A. Svigelj

发明人： Gregory J. Dunn ,  Robert T. Croswell ,  George H. Kumpf ,  John A. Svigelj

IPC分类号： H01Q15/24

CPC分类号： H01Q15/006 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09609

摘要： A high impedance surface (300) has a printed circuit board (302) with a first surface (314) and a second surface (316), and a continuous electrically conductive plate (319) disposed on the second surface (316) of the printed circuit board (302). A plurality of electrically conductive plates (318) is disposed on the first surface (314) of the printed circuit board (302), while a plurality of elements are also provided. Each element comprises at least one of (1) at least one multi-layer inductor (330, 331) electrically coupled between at least two of the electrically conductive plates (318) and embedded within the printed circuit board (302), and (2) at least one capacitor (320) electrically coupled between at least two of the electrically conductive plates (318). The capacitor (320) comprises at least one of (a) a dielectric material (328) disposed between adjacent electrically conductive plates, wherein the dielectric material (328) has a relative dielectric constant greater than 6, and (b) a mezzanine capacitor embedded within the printed circuit board (302).

摘要翻译： 高阻抗表面（300）具有带有第一表面（314）和第二表面（316）的印刷电路板（302）和设置在印刷的第二表面（316）上的连续导电板（319） 电路板（302）。 多个导电板（318）设置在印刷电路板（302）的第一表面（314）上，同时还提供多个元件。 每个元件包括（1）至少一个电耦合在至少两个导电板（318）之间并嵌入印刷电路板（302）内的多层电感器（330,331）中的至少一个，和（2 ）至少一个电耦合在至少两个导电板（318）之间的电容器（320）。 电容器（320）包括设置在相邻导电板之间的（a）介电材料（328）中的至少一个，其中介电材料（328）具有大于6的相对介电常数，以及（b）嵌入的夹层电容器 在印刷电路板（302）内。

公开(公告)号：US07361847B2

公开(公告)日：2008-04-22

申请号：US11323515

申请日：2005-12-30

申请人： Gregory J. Dunn ,  Jaroslaw A. Magera ,  Jovica Savic

发明人： Gregory J. Dunn ,  Jaroslaw A. Magera ,  Jovica Savic

IPC分类号： H05K1/16

CPC分类号： H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09718

摘要： A method is for fabricating an embedded capacitance printed circuit board assembly (400, 1100). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (110). Each capacitance structure (110) includes a crystallized dielectric oxide layer (115) sandwiched between an outer electrode layer (120) and an inner electrode layer (125) in which the two inner electrode layers are electrically connected together. A rivet via (1315) and a stacked via (1110) formed from a button via (910) and a stacked blind via (1111) may be used to electrically connect the two inner electrode layers together. A spindle via (525) may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate (100) that includes two capacitance structures.

摘要翻译： 一种用于制造嵌入式电容印刷电路板组件（400,1100）的方法。 嵌入式电容印刷电路板组件包括两个嵌入式电容结构（110）。 每个电容结构（110）包括夹在两个内部电极层电连接在一起的外部电极层（120）和内部电极层（125）之间的结晶化电介质氧化物层（115）。 可以使用铆钉通孔（1315）和由按钮通孔（910）和堆叠的通孔（1111）形成的堆叠通孔（1110）将两个内部电极层电连接在一起。 主轴通孔（525）可以通过内层和外层形成。 多层印刷电路板可以由包括两个电容结构的电容层压板（100）形成。

公开(公告)号：US20080003414A1

公开(公告)日：2008-01-03

申请号：US11428454

申请日：2006-07-03

申请人： Jaroslaw A. Magera ,  Gregory J. Dunn

发明人： Jaroslaw A. Magera ,  Gregory J. Dunn

IPC分类号： B32B3/00

CPC分类号： H05K3/428 ,  H05K1/116 ,  H05K3/0008 ,  H05K3/0047 ,  H05K3/025 ,  H05K3/205 ,  H05K3/427 ,  H05K2201/09063 ,  H05K2201/09918 ,  H05K2203/1438 ,  Y10T428/24917

摘要： A sequentially laminated printed circuit board having highly reliable vias can be fabricated by pattern plating flanges or via lands on a copper foil, laminating the foil to a prepreg so that the flanges are embedded into the surface of the prepreg, creating via holes in the laminate that are substantially concentric with the individual flanges, plating the via holes with copper, chemically or mechanically milling off a portion of the copper plating and optionally some of the copper foil to reduce the overall thickness of the laminate, and laminating a second and optionally a third prepreg to the laminate. The resulting printed circuit board has the flanges embedded in the surface of the laminate so that the inside wall of the flange is electrically and mechanically attached to the outside wall of the plated through hole barrel.

摘要翻译： 具有高度可靠的通孔的顺序层压的印刷电路板可以通过铜箔上的图案电镀法兰或通孔焊盘来制造，将箔层压到预浸料上，使得凸缘嵌入预浸料的表面中，从而在层压板中形成通孔 其与各个凸缘基本同心，用铜电镀通孔，化学或机械地研磨铜镀层的一部分和任选的一些铜箔以减小层压体的总厚度，并层压第二和任选的 第三预浸料。 所得到的印刷电路板具有嵌入在层压体的表面中的凸缘，使得凸缘的内壁电连接和机械地附接到电镀通孔筒的外壁。

公开(公告)号：US07105913B2

公开(公告)日：2006-09-12

申请号：US10743589

申请日：2003-12-22

申请人： Gregory J. Dunn ,  Scott N. Carney ,  Jovica Savic

发明人： Gregory J. Dunn ,  Scott N. Carney ,  Jovica Savic

IPC分类号： H01L27/082

CPC分类号： H01C7/006 ,  H01C1/148 ,  H01C17/065 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/00

摘要： A technique for fabricating a patterned resistor on a substrate produces a patterned resistor (101, 801, 1001, 1324, 1374) including two conductive end terminations (110, 810, 1010) on the substrate, a pattern of first resistive material (120, 815, 1015) having a first width (125) and a first sheet resistance, and a pattern of second resistive material (205, 820, 1020) having a second width (210) and a second sheet resistance that at least partially overlies the pattern of first resistive material. One of the first and second sheet resistances is a low sheet resistance and the other of the first and second resistances is a high sheet resistance. A ratio of the high sheet resistance to the low sheet resistance is at least ten to one. The pattern having the higher sheet resistance is substantially wider than the pattern having the low sheet resistance. The patterned resistor can be precision trimmed 1225.

摘要翻译： 用于在衬底上制造图案化电阻器的技术产生包括在衬底上的两个导电端接（110,810,1010）的图案化电阻器（101,801,1001,1324,1374），第一电阻材料（120， 具有第一宽度（125）和第一薄层电阻的第二电阻材料（205,820,1020）的图案，以及具有至少部分地覆盖图案的第二宽度（210）和第二薄层电阻的图案 的第一电阻材料。 第一和第二薄层电阻之一是低的薄层电阻，第一和第二电阻中的另一个是高的薄层电阻。 高薄层电阻与低薄层电阻的比例至少为10比1。 具有较高薄层电阻的图案基本上比具有低薄层电阻的图案更宽。 图案化电阻器可精密修整1225。

公开(公告)号：US07038571B2

公开(公告)日：2006-05-02

申请号：US10448993

申请日：2003-05-30

申请人： Gregory J. Dunn ,  Jovica Savic ,  Remy J. Chelini

发明人： Gregory J. Dunn ,  Jovica Savic ,  Remy J. Chelini

IPC分类号： H01C1/012

CPC分类号： H01C17/065 ,  H01C7/005 ,  H05K1/0266 ,  H05K1/095 ,  H05K1/167 ,  H05K3/12 ,  H05K2201/09781 ,  H05K2203/1453

摘要： A printed circuit polymer thick film (PTF) resistor includes tolerance control material that substantially surrounds the resistor body and significantly improves the linearity of resistance vs. resistor length, and significantly reduces resistor-to-resistor and board-to-board fabrication variances. In one embodiment, the tolerance control material is the same metallic material as the printed circuit conductors, and is formed in two finger patterns on each side of the resistor body, each finger pattern connected to one terminal pad of the resistor. A layout cell is used for fabricating the PTF resistor. A method is used for fabricating the PTF resistor.

摘要翻译： 印刷电路聚合物厚膜（PTF）电阻器包括基本上围绕电阻器体的公差控制材料，并且显着地提高了电阻与电阻器长度的线性度，并且显着降低了电阻器对电阻器和板对板制造方差。 在一个实施例中，公差控制材料与印刷电路导体相同的金属材料，并且形成在电阻体两侧的两个指形图案中，每个指状图案连接到电阻器的一个端子焊盘。 布线单元用于制造PTF电阻。 一种制造PTF电阻的方法。

公开(公告)号：US06872468B1

公开(公告)日：2005-03-29

申请号：US10682557

申请日：2003-10-09

申请人： Timothy B. Dean ,  Gregory J. Dunn ,  Remy J. Chelini ,  Claudia V. Gamboa

发明人： Timothy B. Dean ,  Gregory J. Dunn ,  Remy J. Chelini ,  Claudia V. Gamboa

IPC分类号： H05K1/16 ,  H05K3/02 ,  H05K3/38 ,  B21C37/02

CPC分类号： H05K1/162 ,  H05K3/025 ,  H05K3/384 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  Y10T428/12493 ,  Y10T428/1259 ,  Y10T428/12611 ,  Y10T428/12667 ,  Y10T428/12875 ,  Y10T428/12882 ,  Y10T428/24917

摘要： In one embodiment, a peelable circuit board foil (200) has a metal support layer (205) and a conductive metal foil layer (210) bonded by an inorganic release material (215). The conductive metal foil layer has a an exposed surface (212) that is coated with a high temperature anti-oxidant barrier (220) and has a roughness less than 0.05 microns RMS. In a second embodiment, the peelable printed circuit foil (200) has a crystallized dielectric oxide layer (405) disposed on the exposed surface of the conductive metal foil layer and an electrode layer (415) disposed on the crystallized dielectric oxide layer, forming a dielectric peelable circuit board foil (400) that may be adhered to a layer of a flexible or rigid circuit board, after which the metal support layer can be peeled away, leaving a capacitive structure including the metal foil layer, the crystallized dielectric oxide layer, and the electrode layer.

摘要翻译： 在一个实施例中，可剥离电路板箔（200）具有通过无机剥离材料（215）粘合的金属支撑层（205）和导电金属箔层（210）。 导电金属箔层具有涂覆有高温抗氧化剂屏障（220）并具有小于0.05微米RMS的粗糙度的暴露表面（212）。 在第二实施例中，可剥离印刷电路箔（200）具有设置在导电金属箔层的暴露表面上的结晶的电介质氧化物层（405）和设置在结晶的电介质氧化物层上的电极层（415），形成 可以粘附到柔性或刚性电路板的层的介电可剥离电路板箔（400），之后金属支撑层可以被剥离，留下包括金属箔层，结晶化电介质氧化物层， 和电极层。

公开(公告)号：US06777727B2

公开(公告)日：2004-08-17

申请号：US10304429

申请日：2002-11-26

申请人： Gregory J. Dunn ,  Allyson Beuhler ,  David Penunuri

发明人： Gregory J. Dunn ,  Allyson Beuhler ,  David Penunuri

IPC分类号： H01L2980

CPC分类号： G01N29/245 ,  G01N29/022 ,  G01N29/222 ,  G01N2291/0256 ,  G01N2291/0427 ,  H01L27/20

摘要： An exemplary system and method for providing an acoustic plate wave apparatus is disclosed as comprising inter alia: a monocrystalline silicon substrate (200); an amorphous oxide material (220); a monocrystalline perovskite oxide material (230); a monocrystalline piezoelectric material (240); and a flexural plate wave component (250, 270) having an input interdigitated transducer (270), an output interdigitated transducer (250) and an optional support layer (260). Deposition or removal of material on or from an absorptive thin film sensor surface (210), or changes in the mechanical properties of the thin film (210) in contact with various chemical species, or changes in the electrical characteristics of a solvent solution exposed to the thin film (210) generally operate to produce measurable perturbations in the vector quantities (e.g., velocity, etc.) and scalar quantities (e.g., attenuation, etc.) of the acoustic plate modes.

摘要翻译： 公开了一种用于提供声板波装置的示例性系统和方法，其包括：单晶硅衬底（200）; 无定形氧化物材料（220）; 单晶钙钛矿氧化物材料（230）; 单晶压电材料（240）; 以及具有输入交叉换能器（270）的弯曲板波分量（250,270），输出叉指换能器（250）和可选支撑层（260）。 在吸收薄膜传感器表面（210）上或从吸收薄膜传感器表面（210）上沉积或去除材料，或与各种化学物质接触的薄膜（210）的机械性能的变化，或暴露于 薄膜（210）通常用于在声板模式的矢量（例如，速度等）和标量（例如，衰减等）中产生可测量的扰动。