公开(公告)号：US20130078771A1

公开(公告)日：2013-03-28

申请号：US13613858

申请日：2012-09-13

Applicant: Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

Inventor： Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

IPC: H01L21/331

CPC classification number: H01L29/66068 ,  H01L29/1608 ,  H01L29/7395

Abstract: A collector layer having p type is formed on a silicon carbide substrate having n type. A drift layer having n type is formed on a top surface side of the collector layer. A body region provided on the drift layer and having p type, and an emitter region provided on the body region to be separated from the drift layer by the body region and having n type are formed. A bottom surface side of the collector layer is exposed by removing the silicon carbide substrate.

Abstract translation: 具有p型的集电极层形成在具有n型的碳化硅衬底上。 在集电体层的顶面侧形成有n型漂移层。 设置在漂移层上并具有p型的体区，并且形成设置在身体区域上以通过身体区域与移动层分离并具有n型的发射极区域。 通过去除碳化硅衬底来暴露集电极层的底表面侧。

公开(公告)号：US20130075759A1

公开(公告)日：2013-03-28

申请号：US13613838

申请日：2012-09-13

Applicant: Keiji Wada ,  Takeyoshi Masuda ,  Toru Hiyoshi

Inventor： Keiji Wada ,  Takeyoshi Masuda ,  Toru Hiyoshi

IPC: H01L29/161

CPC classification number: H01L21/0475 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7813

Abstract: A first layer has n type conductivity. A second layer is epitaxially formed on the first layer and having p type conductivity. A third layer is on the second layer and having n type conductivity. ND is defined to represent a concentration of a donor type impurity. NA is defined to represent a concentration of an acceptor type impurity. D1 is defined to represent a location in the first layer away from an interface between the first layer and the second layer in a depth direction. D1 in which 1≦ND/NA≦50 is satisfied is within 1 μm therefrom. A gate trench is provided to extend through the third layer and the second layer to reach the first layer. A gate insulating film covers a side wall of the gate trench. A gate electrode is embedded in the gate trench with the gate insulating film interposed therebetween.

Abstract translation: 第一层具有n型导电性。 第二层外延形成在第一层上并具有p型导电性。 第三层位于第二层上，具有n型导电性。 ND被定义为表示供体型杂质的浓度。 NA被定义为表示受体型杂质的浓度。 D1被定义为在深度方向上表示远离第一层和第二层之间的界面的第一层中的位置。 其中满足1＆nlE; ND / NA＆nlE; 50的D1在其1μm以内。 提供栅极沟槽以延伸穿过第三层和第二层以到达第一层。 栅极绝缘膜覆盖栅极沟槽的侧壁。 栅极电极嵌入栅极沟槽中，栅极绝缘膜插入其间。

公开(公告)号：US20130065384A1

公开(公告)日：2013-03-14

申请号：US13613785

申请日：2012-09-13

Applicant: Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

Inventor： Toru Hiyoshi ,  Takeyoshi Masuda ,  Keiji Wada

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/0475 ,  H01L21/3065 ,  H01L21/3081 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7397

Abstract: A mask layer is formed on a silicon carbide layer by a deposition method. The mask layer is patterned. A gate trench having a side wall is formed by removing a portion of the silicon carbide layer by etching using the patterned mask layer as a mask. A gate insulating film is formed on the side wall of the gate trench. A gate electrode is formed on the gate insulating film. The silicon carbide layer has one of hexagonal and cubic crystal types, and the side wall of the gate trench substantially includes one of a{0-33-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.

Abstract translation: 通过沉积方法在碳化硅层上形成掩模层。 掩模层被图案化。 通过使用图案化掩模层作为掩模的蚀刻去除碳化硅层的一部分来形成具有侧壁的栅极沟槽。 栅极绝缘膜形成在栅极沟槽的侧壁上。 在栅极绝缘膜上形成栅电极。 碳化硅层具有六方晶体和立方晶体中的一种，栅极沟槽的侧壁基本上包括{0-33-8}面和{01-1-4}面之一，在硅 碳化物层为六方晶系，并且在碳化硅层为立方晶型的情况下，基本上包含{100}面。

公开(公告)号：US20120326166A1

公开(公告)日：2012-12-27

申请号：US13529602

申请日：2012-06-21

Applicant: Takeyoshi Masuda ,  Shin Harada ,  Keiji Wada ,  Toru Hiyoshi

Inventor： Takeyoshi Masuda ,  Shin Harada ,  Keiji Wada ,  Toru Hiyoshi

IPC: H01L29/24 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7802 ,  H01L21/049 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

Abstract: A substrate has a surface made of a semiconductor having a hexagonal single-crystal structure of polytype 4H. The surface of the substrate is constructed by alternately providing a first plane having a plane orientation of (0-33-8), and a second plane connected to the first plane and having a plane orientation different from the plane orientation of the first plane. A gate insulating film is provided on the surface of the substrate. A gate electrode is provided on the gate insulating film.

Abstract translation: 衬底具有由具有多晶型4H的六方晶单晶结构的半导体制成的表面。 基板的表面通过交替地提供具有（0-33-8）的平面取向的第一平面和连接到第一平面并具有不同于第一平面的平面取向的平面取向的第二平面来构造。 栅极绝缘膜设置在基板的表面上。 在栅极绝缘膜上设置栅电极。

公开(公告)号：US20120228640A1

公开(公告)日：2012-09-13

申请号：US13512456

申请日：2011-07-14

Applicant: Takeyoshi Masuda ,  Shin Harada ,  Misako Honaga ,  Keiji Wada ,  Toru Hiyoshi

Inventor： Takeyoshi Masuda ,  Shin Harada ,  Misako Honaga ,  Keiji Wada ,  Toru Hiyoshi

IPC: H01L29/24 ,  H01L21/04

CPC classification number: H01L29/66068 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/6606 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/8613 ,  H01L29/868

Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes: a substrate having a main surface; and a silicon carbide layer formed on the main surface of the substrate and including a side surface inclined relative to the main surface. The side surface substantially includes a {03-3-8} plane. The side surface includes a channel region.

Abstract translation: 提供了具有稳定特性的高质量半导体器件和制造这种半导体器件的方法。 半导体器件包括：具有主表面的衬底; 以及形成在所述基板的主表面上并且包括相对于所述主表面倾斜的侧表面的碳化硅层。 侧表面基本上包括{03-3-8}平面。 侧面包括通道区域。

公开(公告)号：US20120208368A1

公开(公告)日：2012-08-16

申请号：US13502976

申请日：2011-02-25

Applicant: Takeyoshi Masuda ,  Keiji Wada ,  Satomi Itoh ,  Toru Hiyoshi

Inventor： Takeyoshi Masuda ,  Keiji Wada ,  Satomi Itoh ,  Toru Hiyoshi

IPC: H01L21/31 ,  H01L21/308

CPC classification number: H01L29/7802 ,  H01L21/02057 ,  H01L21/02236 ,  H01L21/02301 ,  H01L21/0445 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/66053 ,  H01L29/66068

Abstract: A method of manufacturing an SiC semiconductor device includes the steps of forming a first oxide film on a first surface of an SiC semiconductor, removing the first oxide film, and forming a second oxide film constituting the SiC semiconductor device on a second surface exposed as a result of removal of the first oxide film in the SiC semiconductor. Between the step of removing the first oxide film and the step of forming a second oxide film, the SiC semiconductor is arranged in an atmosphere cut off from an ambient atmosphere.

Abstract translation: 一种制造SiC半导体器件的方法包括以下步骤：在SiC半导体的第一表面上形成第一氧化物膜，去除第一氧化物膜，以及在第二表面上形成构成SiC半导体器件的第二氧化膜， 去除SiC半导体中第一氧化膜的结果。 在除去第一氧化物膜的步骤和形成第二氧化物膜的步骤之间，将SiC半导体布置在从环境气氛切断的气氛中。

公开(公告)号：US08203151B2

公开(公告)日：2012-06-19

申请号：US12906579

申请日：2010-10-18

Applicant: Takeyoshi Masuda

Inventor： Takeyoshi Masuda

IPC: H01L29/04 ,  H01L29/15 ,  H01L29/00 ,  H01L29/80 ,  H01L29/768

CPC classification number: H01L21/02433 ,  C30B29/36 ,  C30B33/02 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/3247 ,  H01L21/8213 ,  H01L29/0657 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/66068

Abstract: A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot α+cot β) (where α and β are variables that satisfy the relations 0.5≦α, β≦45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：形成SiC膜，在SiC膜的表面形成沟槽，用提供给SiC膜表面的硅对SiC膜进行热处理，并获得多个宏步骤 通过热处理步骤在SiC膜的表面构成通道。 将沟槽的一个周期的长度作为L和沟槽的高度为h，关系L = h（cotα+ cot＆bgr）（其中α和＆bgr是满足关系0.5＆nlE;α， ＆bgr;＆nlE; 45）保持在长度L和高度h之间。 因此，可以提高半导体器件的性能。

公开(公告)号：US08198675B2

公开(公告)日：2012-06-12

申请号：US12515386

申请日：2007-11-16

Applicant: Shin Harada ,  Takeyoshi Masuda

Inventor： Shin Harada ,  Takeyoshi Masuda

IPC: H01L29/161

CPC classification number: H01L29/7813 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02639 ,  H01L21/02658 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068

Abstract: A silicon carbide semiconductor device having excellent performance characteristics and a method of manufacturing the same are obtained. An extended terrace surface is formed at a surface of an initial growth layer on a 4H—SiC substrate by annealing with the initial growth layer covered with an Si film, and then a new growth layer is epitaxially grown on the initial growth layer. A 3C—SiC portion having a polytype stable at a low temperature is grown on the extended terrace surface, and a 4H—SiC portion is grown on the other region. A trench is formed by selectively removing the 3C—SiC portion with the 4H—SiC portion remaining, and a gate electrode of a UMOSFET is formed in the trench. A channel region of the UMOSFET can be controlled to have a low-order surface, and a silicon carbide semiconductor device having high channel mobility and excellent performance characteristics is obtained.

Abstract translation: 获得具有优异性能的碳化硅半导体器件及其制造方法。 通过用覆盖有Si膜的初始生长层退火，在4H-SiC衬底上的初始生长层的表面上形成延伸的台面表面，然后在初始生长层上外延生长新的生长层。 在延伸的台面上生长具有低温稳定性的3C-SiC部分，在其他区域生长4H-SiC部分。 通过选择性地除去具有4H-SiC部分的3C-SiC部分形成沟槽，并且在沟槽中形成UMOSFET的栅电极。 可以将UMOSFET的沟道区域控制为具有低阶表面，并且获得具有高沟道迁移率和优异性能特性的碳化硅半导体器件。

公开(公告)号：US20120007104A1

公开(公告)日：2012-01-12

申请号：US13255031

申请日：2010-04-22

Applicant: Keiji Wada ,  Hideto Tamaso ,  Takeyoshi Masuda ,  Misako Honaga

Inventor： Keiji Wada ,  Hideto Tamaso ,  Takeyoshi Masuda ,  Misako Honaga

IPC: H01L29/24 ,  H01L21/04

CPC classification number: H01L29/7802 ,  H01L21/0455 ,  H01L21/0485 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/808

Abstract: A semiconductor device employing silicon carbide, and the like are provided. In the semiconductor device, even when an electrode material and an upper electrode material are different, a problem does not take place at an interface at which these different types of metals are in contact with each other, thus obtaining high reliability in long-term use.The semiconductor device includes: a contact electrode 16 in contact with silicon carbides 14, 18; and an upper electrode 19 electrically conductive to the contact electrode. The contact electrode 16 is formed of an alloy including titanium, aluminum, and silicon, the upper electrode 19 is formed of aluminum or an aluminum alloy, and the upper electrode achieves the electric conduction to the contact electrode with the upper electrode making contact with the contact electrode.

Abstract translation: 提供了使用碳化硅的半导体器件等。 在半导体装置中，即使电极材料和上部电极材料不同，在这些不同类型的金属彼此接触的界面处也不会发生问题，因此在长期使用中获得高可靠性 。 半导体器件包括：与碳化硅14,18接触的接触电极16; 以及与接触电极导电的上电极19。 接触电极16由包括钛，铝和硅的合金形成，上电极19由铝或铝合金形成，上电极实现与接触电极的导电，上电极与 接触电极。

公开(公告)号：US20110186862A1

公开(公告)日：2011-08-04

申请号：US13063083

申请日：2009-02-03

Applicant: Shin Harada ,  Takeyoshi Masuda ,  Keiji Wada ,  Masato Tsumori

Inventor： Shin Harada ,  Takeyoshi Masuda ,  Keiji Wada ,  Masato Tsumori

IPC: H01L29/24 ,  H01L21/20 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L29/1608 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/3003 ,  H01L21/324 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/94

Abstract: There is provided a silicon carbide semiconductor device having excellent electrical characteristics such as channel mobility, and a method for manufacturing the same. A semiconductor device includes a substrate made of silicon carbide and having an off-angle of greater than or equal to 50° and less than or equal to 65° with respect to a surface orientation of {0001}, a p-type layer serving as a semiconductor layer, and an oxide film serving as an insulating film. The p-type layer is formed on the substrate and is made of silicon carbide. The oxide film is formed to contact with a surface of the p-type layer. A maximum value of the concentration of nitrogen atoms in a region within 10 nm of an interface between the semiconductor layer and the insulating film (interface between a channel region and the oxide film) is greater than or equal to 1×1021 cm−3.

Abstract translation: 提供了具有优异的电特性如沟道迁移率的碳化硅半导体器件及其制造方法。 半导体器件包括相对于{0001}的表面取向具有大于或等于50°且小于或等于65°的偏角度的碳化硅制成的衬底，用作 半导体层和用作绝缘膜的氧化膜。 p型层形成在基板上，由碳化硅制成。 氧化膜形成为与p型层的表面接触。 半导体层与绝缘膜（沟道区域和氧化物膜之间的界面）的界面的10nm以内的区域的氮原子的浓度的最大值为1×1021cm-3以上。