公开(公告)号：US20230282712A1

公开(公告)日：2023-09-07

申请号：US17804971

申请日：2022-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Yen-Tien Tung ,  Ji-Cheng Chen ,  Weng Chang ,  Chi On Chui

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49 ,  H01L27/088

CPC classification number: H01L29/401 ,  H01L29/66742 ,  H01L29/66545 ,  H01L21/28088 ,  H01L29/4908 ,  H01L27/088 ,  H01L29/78696

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, with the semiconductor region being exposed to the trench, forming a gate dielectric layer extending into the trench, and depositing a work-function tuning layer on the gate dielectric layer. The work-function tuning layer comprises aluminum and carbon. The method further includes depositing a p-type work-function layer over the work-function tuning layer, and performing a planarization process to remove excess portions of the p-type work-function layer, the work-function tuning layer, and the gate dielectric layer to form a gate stack.

公开(公告)号：US11699740B2

公开(公告)日：2023-07-11

申请号：US17190267

申请日：2021-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  C23C18/16

CPC classification number: H01L29/66545 ,  C23C18/1657 ,  H01L21/823871 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66742

Abstract: Embodiments utilize an electro-chemical process to deposit a metal gate electrode in a gate opening in a gate replacement process for a nanosheet FinFET device. Accelerators and suppressors may be used to achieve a bottom-up deposition for a fill material of the metal gate electrode.

公开(公告)号：US20230066477A1

公开(公告)日：2023-03-02

申请号：US17462233

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/51 ,  H01L29/40

Abstract: Embodiments include a device and method of forming a device, such as a nano-FET transistor, including a first nanostructure. A gate dielectric is formed around the first nanostructure. A gate electrode is formed over the gate dielectric, and the gate electrode includes a first work function metal. In the gate electrode, a first metal residue is formed at an interface between the gate dielectric and the first work function metal as a result of a treatment process performed prior to forming the first work function metal. The first metal residue has a metal element that is different than a metal element of the first work function metal.

公开(公告)号：US20230020099A1

公开(公告)日：2023-01-19

申请号：US17648152

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui ,  Chun-I Wu ,  Huang-Lin Chao

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/49 ,  H01L21/285 ,  H01L21/28

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the silicon-containing layer, and the gate dielectric layer forming a gate stack.

公开(公告)号：US20220375798A1

公开(公告)日：2022-11-24

申请号：US17882165

申请日：2022-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49

Abstract: A method includes depositing a first conductive layer over a gate dielectric layer; depositing a first work function tuning layer over the first conductive layer; selectively removing the first work function tuning layer from over a first region of the first conductive layer; doping the first work function tuning layer with a dopant; and after doping the first work function tuning layer performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function tuning layer. The first treatment process etches the first conductive layer at a greater rate than the first work function tuning layer.

公开(公告)号：US20220359654A1

公开(公告)日：2022-11-10

申请号：US17813980

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device including a barrier layer surrounding a work function metal layer and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a second channel region over the first channel region; gate dielectric layers surrounding the first channel region and the second channel region; work function metal layers surrounding the gate dielectric layers; and barrier layers surrounding the work function metal layers, a first barrier layer surrounding the first channel region being merged with a second barrier layer surrounding the second channel region.

公开(公告)号：US20220352336A1

公开(公告)日：2022-11-03

申请号：US17869430

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/10 ,  H01L21/28 ,  H01L29/06

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type work function metal; a barrier material over the first p-type work function metal; and a second p-type work function metal over the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal.

公开(公告)号：US11489059B2

公开(公告)日：2022-11-01

申请号：US16741767

申请日：2020-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Weng Chang ,  Chi-On Chui

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/285 ,  H01L29/51

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate strip disposed over the substrate. The gate strip includes a high-k layer disposed over the substrate, an N-type work function metal layer disposed over the high-k layer, and a barrier layer disposed over the N-type work function metal layer. The barrier layer includes at least one first film containing TiAlN, TaAlN or AlN.

公开(公告)号：US20220336591A1

公开(公告)日：2022-10-20

申请号：US17854244

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/40 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. The gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal.

公开(公告)号：US20220093770A1

公开(公告)日：2022-03-24

申请号：US17190267

申请日：2021-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  C23C18/16

Abstract: Embodiments utilize an electro-chemical process to deposit a metal gate electrode in a gate opening in a gate replacement process for a nanosheet FinFET device. Accelerators and suppressors may be used to achieve a bottom-up deposition for a fill material of the metal gate electrode.