公开(公告)号：US11445104B2

公开(公告)日：2022-09-13

申请号：US16822424

申请日：2020-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Shu Huang ,  Ming Chyi Liu ,  Tung-He Chou

IPC: H01L29/00 ,  H04N5/232 ,  G03B13/36 ,  H04N5/247 ,  G01S3/00 ,  H01L21/00 ,  G06V10/40 ,  G06V10/75 ,  G06V40/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/3213 ,  H04N5/225 ,  H04N5/262

Abstract: Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.

公开(公告)号：US11430956B2

公开(公告)日：2022-08-30

申请号：US16578304

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00 ,  H01L27/24

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.

公开(公告)号：US11411086B2

公开(公告)日：2022-08-09

申请号：US16821247

申请日：2020-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kaochao Chen ,  Chia-Cheng Ho ,  Ming Chyi Liu

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78

Abstract: An integrated chip includes a field plate overlying an isolation structure. A gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an upper surface of the gate electrode to a front-side of the substrate. The etch stop layer overlies a drift region disposed between the source region and the drain region. The field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate extends from a top surface of the first ILD layer to an upper surface of the etch stop layer. The isolation structure is disposed within the substrate and extends from the front-side of the substrate to a point below the front-side of the substrate. The isolation structure is disposed laterally between the gate electrode and the drain region.

公开(公告)号：US11374000B2

公开(公告)日：2022-06-28

申请号：US16814142

申请日：2020-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Liang Lee ,  Ming Chyi Liu ,  Shih-Chang Liu

IPC: H01L27/08 ,  H01L27/108 ,  H01L49/02

Abstract: Various embodiments of the present application are directed towards a semiconductor device comprising a trench capacitor, the trench capacitor comprising a plurality of lateral protrusions. In some embodiments, the trench capacitor comprises a dielectric structure over a substrate. The dielectric structure may comprise a plurality of dielectric layers overlying the substrate. The dielectric structure may comprise a plurality of lateral recesses. In some embodiments, the plurality of lateral protrusions extend toward and fill the plurality of lateral recesses. By forming the trench capacitor with the plurality of lateral protrusions filling the plurality of lateral recesses, the surface area of the capacitor is increased without increasing the depth of the trench. As a result, greater capacitance values may be achieved without necessarily increasing the depth of the trench and thus, without necessarily increasing the size of the semiconductor device.

公开(公告)号：US11239245B2

公开(公告)日：2022-02-01

申请号：US16800167

申请日：2020-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Sheng Huang ,  Ming Chyi Liu ,  Chih-Pin Huang

IPC: H01L27/11521 ,  H01L23/528 ,  H01L23/522 ,  H01L29/788 ,  H01L21/768 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

公开(公告)号：US11217596B2

公开(公告)日：2022-01-04

申请号：US16359027

申请日：2019-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Chen ,  Ming Chyi Liu ,  Shih-Chang Liu

IPC: H01L27/11517 ,  H01L27/11563

Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.

公开(公告)号：US11158593B2

公开(公告)日：2021-10-26

申请号：US16829267

申请日：2020-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Bin Chen ,  Chia-Shiung Tsai ,  Ming Chyi Liu ,  Eugene Chen

IPC: H01L23/12 ,  H01L23/48 ,  H01L21/00 ,  H01L21/28 ,  H01L23/00 ,  H01S5/183 ,  H01S5/343 ,  H01S5/0234 ,  H01S5/02355 ,  H01L25/075 ,  H01L33/46 ,  H01L25/065

Abstract: Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.

公开(公告)号：US20210288047A1

公开(公告)日：2021-09-16

申请号：US16814142

申请日：2020-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Liang Lee ,  Ming Chyi Liu ,  Shih-Chang Liu

IPC: H01L27/08 ,  H01L49/02

Abstract: Various embodiments of the present application are directed towards a semiconductor device comprising a trench capacitor, the trench capacitor comprising a plurality of lateral protrusions. In some embodiments, the trench capacitor comprises a dielectric structure over a substrate. The dielectric structure may comprise a plurality of dielectric layers overlying the substrate. The dielectric structure may comprise a plurality of lateral recesses. In some embodiments, the plurality of lateral protrusions extend toward and fill the plurality of lateral recesses. By forming the trench capacitor with the plurality of lateral protrusions filling the plurality of lateral recesses, the surface area of the capacitor is increased without increasing the depth of the trench. As a result, greater capacitance values may be achieved without necessarily increasing the depth of the trench and thus, without necessarily increasing the size of the semiconductor device.

公开(公告)号：US20210167236A1

公开(公告)日：2021-06-03

申请号：US17148657

申请日：2021-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Lee-Chuan Tseng ,  Ming Chyi Liu ,  Po-Chun Liu

IPC: H01L31/0352 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/105 ,  H01L31/18

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. An epitaxial pillar of SiGe or Ge extends upward from the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric layer is arranged over an upper surface of the substrate and is disposed around the lower epitaxial region to extend over outer edges of the well region. The dielectric layer has inner sidewalls that contact outer sidewalls of the epitaxial pillar. A dielectric sidewall structure has a bottom surface that rests on an upper surface of the dielectric layer and has inner sidewalls that extend continuously from the upper surface of the dielectric layer to a top surface of the epitaxial pillar.

公开(公告)号：US20210066451A1

公开(公告)日：2021-03-04

申请号：US16921075

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Bin Chen ,  Ming Chyi Liu

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate and a drain region disposed within the substrate. The drain region is separated from the source region along a first direction. A drift region is disposed within the substrate between the source region and the drain region, and a plurality of isolation structures are disposed within the drift region. A gate electrode is disposed within the substrate. The gate electrode has a base region disposed between the source region and the drift region and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of isolation structures.