公开(公告)号：US11749587B2

公开(公告)日：2023-09-05

申请号：US17855902

申请日：2022-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam Kim ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/481 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having a first surface on which an active region is disposed, and a second surface opposite the first surface, a buried conductive line extending in one direction and having a portion buried in the active region, an insulating portion covering the buried conductive line, a contact structure disposed on the insulating portion and connected to the buried conductive line, a through-hole extending from the second surface to the insulating portion and exposing the buried portion of the buried conductive line, an insulating isolation film disposed on a side surface of the buried conductive line and exposing a bottom surface of the buried portion and a side surface adjacent to the bottom surface, a through-via contacting the bottom surface and the adjacent side surface of the buried conductive line, an insulating liner surrounding the through-via.

公开(公告)号：US11616036B2

公开(公告)日：2023-03-28

申请号：US17694035

申请日：2022-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee Jang ,  Seokho Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Kyuha Lee

IPC: H01L27/146 ,  H01L23/00

Abstract: A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.

公开(公告)号：US11348892B2

公开(公告)日：2022-05-31

申请号：US16854114

申请日：2020-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyung Park ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Kyuha Lee ,  Joohee Jang

IPC: H01L27/30 ,  H01L23/00 ,  H01L27/28 ,  H01L27/146

Abstract: A semiconductor device includes a first adsorption layer, a first bonding layer, a second bonding layer, and a second adsorption layer stacked on a first substrate, and a conductive pattern structure penetrating through the first adsorption layer, the first bonding layer, the second bonding layer and the second adsorption layer. The first and second bonding layers are in contact with each other, and each of the first and second adsorption layers includes a low-K dielectric material.

公开(公告)号：US20220037273A1

公开(公告)日：2022-02-03

申请号：US17206337

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyung Park ,  Seokho Kim ,  Hoonjoo Na ,  Seongmin Son ,  Kyuha Lee ,  Yikoan Hong

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures.

公开(公告)号：US11152317B2

公开(公告)日：2021-10-19

申请号：US16404841

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il Choi ,  Pil-Kyu Kang ,  Hoechul Kim ,  Hoonjoo Na ,  Jaehyung Park ,  Seongmin Son

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L27/146

Abstract: A semiconductor device and a semiconductor package, the device including a pad interconnection structure that penetrates a first buffer dielectric layer and a second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin, the pad interconnection structure includes a central part, a first intermediate part surrounding the central part; a second intermediate part surrounding the first intermediate part, and an outer part surrounding the second intermediate part, a grain size of the outer part is less than a grain size of the second intermediate part, the grain size of the second intermediate part is less than a grain size of the first intermediate part, and the grain size of the first intermediate part is less than a grain size of the central part.

公开(公告)号：US10950470B2

公开(公告)日：2021-03-16

申请号：US16397552

申请日：2019-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taeyeong Kim ,  Minsoo Han ,  Jun Hyung Kim ,  Hoonjoo Na ,  Kwangjin Moon

IPC: H01L21/67 ,  H01L21/687 ,  H01L21/683

Abstract: A substrate bonding apparatus includes a lower chuck that receives a lower substrate and an upper chuck disposed above the lower chuck. An upper substrate is fixed to the upper chuck. The upper chuck and the lower chuck bond the upper substrate to the lower substrate. The upper chuck has an upper convex surface toward the lower chuck. The upper convex surface includes a plurality of first ridges and a plurality of first valleys disposed alternately along an azimuthal direction.

公开(公告)号：US20210057371A1

公开(公告)日：2021-02-25

申请号：US16854114

申请日：2020-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyung Park ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Kyuha Lee ,  Joohee Jang

IPC: H01L23/00 ,  H01L27/30 ,  H01L27/28

Abstract: A semiconductor device includes a first adsorption layer, a first bonding layer, a second bonding layer, and a second adsorption layer stacked on a first substrate, and a conductive pattern structure penetrating through the first adsorption layer, the first bonding layer, the second bonding layer and the second adsorption layer. The first and second bonding layers are in contact with each other, and each of the first and second adsorption layers includes a low-K dielectric material.

公开(公告)号：US20210057263A1

公开(公告)日：2021-02-25

申请号：US16892492

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoechul Kim ,  Taeyeong Kim ,  Hakjun ` Lee ,  Hoonjoo Na

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/50

Abstract: A substrate bonding apparatus includes a first bonding chuck configured to support a first substrate and a second bonding chuck configured to support a second substrate such that the second substrate faces the first substrate. The first bonding chuck includes a first base, a first deformable plate on the first base and configured to support the first substrate and configured to be deformed such that a distance between the first base and the first deformable plate is varied, and a first piezoelectric sheet on the first deformable plate and configured to be deformed in response to power applied thereto to deform the first deformable plate.

公开(公告)号：US20210028112A1

公开(公告)日：2021-01-28

申请号：US16863126

申请日：2020-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam Kim ,  Kwangjin Moon ,  Hojin Lee ,  Pilkyu Kang ,  Hoonjoo Na

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L23/48 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a first surface and a second surface opposite to each other, and having an active region located on the first surface and defined by a first isolation region; a plurality of active fins arranged on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the plurality of active fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the buried conductive wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.

公开(公告)号：US10892342B2

公开(公告)日：2021-01-12

申请号：US16803130

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Jae-Jung Kim ,  Jinkyu Jang ,  Sangyong Kim ,  Hoonjoo Na ,  Dongsoo Lee ,  Sangjin Hyun

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L27/11 ,  H01L21/28 ,  B82Y10/00

Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.