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公开(公告)号:US11887841B2
公开(公告)日:2024-01-30
申请号:US17194575
申请日:2021-03-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyuha Lee , Joohee Jang , Seokho Kim , Hoonjoo Na , Jaehyung Park , Seongmin Son , Yikoan Hong
IPC: H01L25/065 , H01L23/538
CPC classification number: H01L25/0657 , H01L23/5385 , H01L23/5386
Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, first main connection pad structures, and first dummy connection pad structures. The first main connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a first main pitch in a first direction parallel to a top surface of the first semiconductor chip, wherein each of the first main connection pad structures includes a first connection pad electrically connected to the first semiconductor chip, and a second connection pad electrically connected to the second semiconductor chip and contacting the first connection pad. The first dummy connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip, are arranged to be apart from the first main connection pad structures, and are arranged to be apart from each other by a first dummy pitch in the first direction, the first dummy pitch being greater than the first main pitch.
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公开(公告)号:USD809726S1
公开(公告)日:2018-02-06
申请号:US29561979
申请日:2016-04-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Designer: Chanyeong Park , Hyunuk Park , Junwon Seo , Kyuha Lee , Seungil Han , Youngmi Kim , Jeawon Lee
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公开(公告)号:US12142588B2
公开(公告)日:2024-11-12
申请号:US18126205
申请日:2023-03-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Joohee Jang , Seokho Kim , Hoonjoo Na , Jaehyung Park , Kyuha Lee
IPC: H01L27/146 , H01L23/00
Abstract: A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.
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公开(公告)号:US20230238343A1
公开(公告)日:2023-07-27
申请号:US18126205
申请日:2023-03-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Joohee Jang , Seokho Kim , Hoonjoo Na , Jaehyung Park , Kyuha Lee
IPC: H01L23/00 , H01L27/146
CPC classification number: H01L24/08 , H01L24/03 , H01L24/05 , H01L24/27 , H01L24/32 , H01L27/14636 , H01L2224/03831 , H01L2224/03845 , H01L2224/05018 , H01L2224/05022 , H01L2224/05026 , H01L2224/05073 , H01L2224/05571 , H01L2224/08057 , H01L2224/08145 , H01L2224/32145
Abstract: A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.
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公开(公告)号:US11362067B2
公开(公告)日:2022-06-14
申请号:US16855352
申请日:2020-04-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyuha Lee , Pilkyu Kang , Seokho Kim , Hoonjoo Na , Kwangjin Moon , Jaehyung Park , Joohee Jang , Yikoan Hong
IPC: H01L25/065 , H01L23/00
Abstract: A method of manufacturing a semiconductor device according to example embodiments includes: sequentially forming first through third insulating layers on a substrate; forming an opening by etching the first through third insulating layers; forming a conductive layer configured in the opening; forming a fourth insulating layer in the opening after the forming of the conductive layer; and removing a portion of an edge region of the substrate after the forming of the fourth insulating layer.
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公开(公告)号:US11957290B2
公开(公告)日:2024-04-16
申请号:US16858249
申请日:2020-04-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Johannes Büsing , Kyuha Lee , Jusik Kim
CPC classification number: A47L15/4223 , A47L15/10 , A47L15/4217
Abstract: A dishwasher includes a main body, a tub provided inside the main body and configured to form a washing chamber, a machine room formed under the tub, a drain hose configured to discharge washing water stored in the washing chamber, and a hose fixer disposed on a side surface of the tub and configured to fix at least a part of the drain hose, and the drain hose further includes a first coupler coupled to one side of the machine room and a second coupler coupled to the hose fixer, and the first coupler includes an insertion part provided to extend in a longitudinal direction of the first coupler to be inserted to the one side of the machine room to couple the first coupler to the one side of the machine room.
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公开(公告)号:US11532581B2
公开(公告)日:2022-12-20
申请号:US17158450
申请日:2021-01-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Uidam Jung , Hyoungyol Mun , Sangjun Park , Kyuha Lee
IPC: H01L23/00 , H01L25/065 , H01L25/18
Abstract: A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads.
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公开(公告)号:US20210066250A1
公开(公告)日:2021-03-04
申请号:US16855352
申请日:2020-04-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyuha Lee , Pilkyu Kang , Seokho Kim , Hoonjoo Na , Kwangjin Moon , Jaehyung Park , Joohee Jang , Yikoan Hong
IPC: H01L25/065 , H01L23/00
Abstract: A method of manufacturing a semiconductor device according to example embodiments includes: sequentially forming first through third insulating layers on a substrate; forming an opening by etching the first through third insulating layers; forming a conductive layer configured in the opening; forming a fourth insulating layer in the opening after the forming of the conductive layer; and removing a portion of an edge region of the substrate after the forming of the fourth insulating layer.
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公开(公告)号:US11616036B2
公开(公告)日:2023-03-28
申请号:US17694035
申请日:2022-03-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Joohee Jang , Seokho Kim , Hoonjoo Na , Jaehyung Park , Kyuha Lee
IPC: H01L27/146 , H01L23/00
Abstract: A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.
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公开(公告)号:US11348892B2
公开(公告)日:2022-05-31
申请号:US16854114
申请日:2020-04-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jaehyung Park , Seokho Kim , Hoonjoo Na , Kwangjin Moon , Kyuha Lee , Joohee Jang
IPC: H01L27/30 , H01L23/00 , H01L27/28 , H01L27/146
Abstract: A semiconductor device includes a first adsorption layer, a first bonding layer, a second bonding layer, and a second adsorption layer stacked on a first substrate, and a conductive pattern structure penetrating through the first adsorption layer, the first bonding layer, the second bonding layer and the second adsorption layer. The first and second bonding layers are in contact with each other, and each of the first and second adsorption layers includes a low-K dielectric material.
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