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    HOST-BASED AND CLIENT-BASED COMMAND SCHEDULING IN LARGE BANDWIDTH MEMORY SYSTEMS
    42.
    发明申请
    HOST-BASED AND CLIENT-BASED COMMAND SCHEDULING IN LARGE BANDWIDTH MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20190079677A1

    公开(公告)日：2019-03-14

    申请号：US15821686

    申请日：2017-11-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG ,  Robert BRENNAN

    IPC: G06F3/06

    Abstract: A high-bandwidth memory (HBM) system includes an HBM device and a logic circuit. The logic circuit receives a first command from the host device and converts the received first command to a processing-in-memory (PIM) command that is sent to the HBM device through the second interface. A time between when the first command is received from the host device and when the HBM system is ready to receive another command from the host device is deterministic. The logic circuit further receives a fourth command and a fifth command from the host device. The fifth command requests time-estimate information relating to a time between when the fifth command is received and when the HBM system is ready to receive another command from the host device. The time-estimate information includes a deterministic period of time and an estimated period of time for a non-deterministic period of time.

    TRANSACTION-BASED HYBRID MEMORY MODULE
    45.
    发明申请
    TRANSACTION-BASED HYBRID MEMORY MODULE 审中-公开
    基于事务的混合存储器模块

    公开(公告)号：US20170060434A1

    公开(公告)日：2017-03-02

    申请号：US14947145

    申请日：2015-11-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mu-Tien CHANG ,  Hongzhong ZHENG ,  Dimin NIU

    IPC: G06F3/06 ,  G06F12/10 ,  G06F12/08

    CPC classification number: G06F3/0679 ,  G06F3/061 ,  G06F3/0656 ,  G06F13/1668

    Abstract: A hybrid memory module includes a dynamic random access memory (DRAM) cache, a flash storage, and a memory controller. The DRAM cache includes one or more DRAM devices and a DRAM controller, and the flash storage includes one or more flash devices and a flash controller. The memory controller interfaces with the DRAM controller and the flash controller.

    Abstract translation: 混合存储器模块包括动态随机存取存储器（DRAM）高速缓存，闪存存储器和存储器控制器。 DRAM高速缓存包括一个或多个DRAM设备和DRAM控制器，并且闪存存储器包括一个或多个闪存设备和闪存控制器。 存储器控制器与DRAM控制器和闪存控制器接口。

    MEMORY SYSTEM ARCHITECTURE
    46.
    发明申请
    MEMORY SYSTEM ARCHITECTURE 有权
    存储系统架构

    公开(公告)号：US20170017399A1

    公开(公告)日：2017-01-19

    申请号：US14932953

    申请日：2015-11-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hongzhong ZHENG ,  SUHAS ,  Chaohong HU

    IPC: G06F3/06

    CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0673 ,  G06F13/16

    Abstract: An embodiment includes a module, comprising: a memory bus interface; circuitry; and a controller coupled to the memory bus interface and the circuitry, and configured to: collect meta-data associated with the circuitry; and enable access to the meta-data in response to a memory access received through the memory bus interface.

    Abstract translation: 实施例包括模块，包括：存储器总线接口; 电路; 以及控制器，其耦合到所述存储器总线接口和所述电路，并且被配置为：收集与所述电路相关联的元数据; 并且响应于通过存储器总线接口接收到的存储器访问而允许访问元数据。

    SPACE-MULTIPLEXING DRAM-BASED RECONFIGURABLE LOGIC
    47.
    发明申请
    SPACE-MULTIPLEXING DRAM-BASED RECONFIGURABLE LOGIC 有权
    空间复用基于DRAM的可重新配置逻辑

    公开(公告)号：US20160173103A1

    公开(公告)日：2016-06-16

    申请号：US14838348

    申请日：2015-08-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mingyu GAO ,  Hongzhong ZHENG ,  Krishna T. MALLADI

    IPC: H03K19/177

    CPC classification number: H03K19/1776 ,  H01L25/18 ,  H01L25/50 ,  H01L2924/0002 ,  H03K19/17728 ,  H03K19/17736 ,  H01L2924/00

    Abstract: According to one general aspect, an apparatus may include a random access memory array that, in turn, includes a reconfigurable look-up table. The reconfigurable look-up table may include memory cells configured to simultaneously store a plurality of look-up tables, wherein each look-up table is associated with a respective logic function. The reconfigurable look-up table may include a local row decoder configured to activate one or more rows of memory cells based upon a set of input signals. The reconfigurable look-up table may be configured to perform one logic function at a time, and wherein the logic function is dynamically selected. The plurality of look up tables stored in the memory cells may be configured to be dynamically altered via a write operation to the random access memory array.

    Abstract translation: 根据一个一般方面，装置可以包括随机存取存储器阵列，其又包括可重新配置的查找表。 可重构查找表可以包括被配置为同时存储多个查找表的存储器单元，其中每个查找表与相应的逻辑功能相关联。 可重构查找表可以包括配置成基于一组输入信号来激活一行或多行存储器单元的本地行解码器。 可重构查找表可以被配置为一次执行一个逻辑功能，并且其中逻辑功能被动态地选择。 存储在存储器单元中的多个查找表可以被配置为通过写入操作来动态地改变到随机存取存储器阵列。

    UNIFIED OBJECT INTERFACE FOR MEMORY AND STORAGE SYSTEM
    48.
    发明申请
    UNIFIED OBJECT INTERFACE FOR MEMORY AND STORAGE SYSTEM 审中-公开
    用于存储和存储系统的统一对象接口

    公开(公告)号：US20160170649A1

    公开(公告)日：2016-06-16

    申请号：US14733895

    申请日：2015-06-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Rakesh RAMESH ,  Hongzhong ZHENG ,  Krishna T. MALLADI

    IPC: G06F3/06

    CPC classification number: G06F11/0718 ,  G06F3/0608 ,  G06F3/0623 ,  G06F3/0641 ,  G06F3/0667 ,  G06F3/0679 ,  G06F3/0688

    Abstract: A data structure and a mechanism to manage storage of objects is disclosed. The data structure can be used to manage storage of objects on any storage device, whether in memory or some other storage device. Given an object ID (OID) for an object, the system can identify a tuple that includes a device ID and an address. The device ID specifies the device storing the object, and the address specifies the address on the device where the object is stored. The application can then access the object using the device ID and the address.

    Abstract translation: 公开了一种用于管理对象存储的数据结构和机制。 数据结构可用于管理任何存储设备上的对象的存储，无论是在存储器还是其他存储设备中。 给定对象的对象ID（OID），系统可以识别包含设备ID和地址的元组。 设备ID指定存储对象的设备，地址指定存储对象的设备上的地址。 然后，应用程序可以使用设备ID和地址访问对象。

    COMPLETELY UTILIZING HAMMING DISTANCE FOR SECDED BASED ECC DIMMS
    49.
    发明申请
    COMPLETELY UTILIZING HAMMING DISTANCE FOR SECDED BASED ECC DIMMS 有权
    完全使用基于密码的ECC DIMMS的HAMMING距离

    公开(公告)号：US20160134307A1

    公开(公告)日：2016-05-12

    申请号：US14640005

    申请日：2015-03-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chaohong HU ,  Hongzhong ZHENG ,  Prashant Jayaprakash NAIR

    IPC: H03M13/29 ,  G11C29/52 ,  G06F11/10

    CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C2029/0411 ,  H03M13/19

    Abstract: In an Error Correction Code (ECC)-based memory, a Single Error Correction Double Error Detection (SECDED) scheme is used with data aggregation to correct more than one error in a memory word received in a memory burst. By completely utilizing the Hamming distance of the SECDED (128,120) code, 8 ECC bits can potentially correct one error in 120 data bits. Each memory burst is effectively “expanded” from its actual 64 data bits to 120 data bits by “sharing” additional 56 data bits from all of the other related bursts. When a cache line of 512 bits is read, the SECDED (128,120) code is used in conjunction with all the received 64 ECC bits to correct more than one error in the actual 64 bits of data in a memory word. The data mapping of the present disclosure translates to a higher rate of error correction than the existing (72,64) SECDED code.

    Abstract translation: 在基于纠错码（ECC）的存储器中，使用单纠错双重错误检测（SECDED）方案进行数据聚合，以校正存储器突发中接收的存储器字中的多于一个错误。 通过完全利用SECDED（128,120）码的汉明距离，8个ECC位可以潜在地纠正120个数据位中的一个错误。 每个存储器突发通过从所有其他相关突发中“共享”附加的56个数据位，从其实际的64个数据位被有效地“扩展”到120个数据位。 当读取512位的高速缓存行时，SECDED（128,120）代码与所有接收的64个ECC位结合使用，以校正存储器字中实际64位数据中的多于一个错误。 本公开的数据映射转化为比现有（72,64）SECDED代码更高的纠错率。

    HBM RAS CACHE ARCHITECTURE
    50.
    发明申请
    HBM RAS CACHE ARCHITECTURE 有权

    公开(公告)号：US20220035719A1

    公开(公告)日：2022-02-03

    申请号：US17499852

    申请日：2021-10-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dimin NIU ,  Krishna MALLADI ,  Hongzhong ZHENG

    IPC: G06F11/20 ,  G06F11/10

    Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies that include a memory cell die and a logic die. The memory cell die may be configured to store data at a memory address. The logic die may include an interface to the stacked integrated circuit dies and configured to communicate memory accesses between the memory cell die and at least one external device. The logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. The reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. The reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory.

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