公开(公告)号：US20170017399A1

公开(公告)日：2017-01-19

申请号：US14932953

申请日：2015-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongzhong ZHENG ,  SUHAS ,  Chaohong HU

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0673 ,  G06F13/16

Abstract: An embodiment includes a module, comprising: a memory bus interface; circuitry; and a controller coupled to the memory bus interface and the circuitry, and configured to: collect meta-data associated with the circuitry; and enable access to the meta-data in response to a memory access received through the memory bus interface.

Abstract translation: 实施例包括模块，包括：存储器总线接口; 电路; 以及控制器，其耦合到所述存储器总线接口和所述电路，并且被配置为：收集与所述电路相关联的元数据; 并且响应于通过存储器总线接口接收到的存储器访问而允许访问元数据。

公开(公告)号：US20160134307A1

公开(公告)日：2016-05-12

申请号：US14640005

申请日：2015-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chaohong HU ,  Hongzhong ZHENG ,  Prashant Jayaprakash NAIR

IPC: H03M13/29 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C2029/0411 ,  H03M13/19

Abstract: In an Error Correction Code (ECC)-based memory, a Single Error Correction Double Error Detection (SECDED) scheme is used with data aggregation to correct more than one error in a memory word received in a memory burst. By completely utilizing the Hamming distance of the SECDED (128,120) code, 8 ECC bits can potentially correct one error in 120 data bits. Each memory burst is effectively “expanded” from its actual 64 data bits to 120 data bits by “sharing” additional 56 data bits from all of the other related bursts. When a cache line of 512 bits is read, the SECDED (128,120) code is used in conjunction with all the received 64 ECC bits to correct more than one error in the actual 64 bits of data in a memory word. The data mapping of the present disclosure translates to a higher rate of error correction than the existing (72,64) SECDED code.

Abstract translation: 在基于纠错码（ECC）的存储器中，使用单纠错双重错误检测（SECDED）方案进行数据聚合，以校正存储器突发中接收的存储器字中的多于一个错误。 通过完全利用SECDED（128,120）码的汉明距离，8个ECC位可以潜在地纠正120个数据位中的一个错误。 每个存储器突发通过从所有其他相关突发中“共享”附加的56个数据位，从其实际的64个数据位被有效地“扩展”到120个数据位。 当读取512位的高速缓存行时，SECDED（128,120）代码与所有接收的64个ECC位结合使用，以校正存储器字中实际64位数据中的多于一个错误。 本公开的数据映射转化为比现有（72,64）SECDED代码更高的纠错率。

公开(公告)号：US20180129553A1

公开(公告)日：2018-05-10

申请号：US15865250

申请日：2018-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chaohong HU ,  Hongzhong ZHENG ,  Uksong KANG ,  Zhan PING

IPC: G06F11/10

Abstract: An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface.

公开(公告)号：US20180113621A1

公开(公告)日：2018-04-26

申请号：US15847916

申请日：2017-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongzhong ZHENG ,  SUHAS ,  Chaohong HU

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0673 ,  G06F13/16

Abstract: An embodiment includes a module, comprising: a memory bus interface; circuitry; and a controller coupled to the memory bus interface and the circuitry, and configured to: collect meta-data associated with the circuitry; and enable access to the meta-data in response to a memory access received through the memory bus interface.

公开(公告)号：US20160266975A1

公开(公告)日：2016-09-15

申请号：US14863446

申请日：2015-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chaohong HU ,  Hongzhong ZHENG ,  Dimin NIU

IPC: G06F11/10 ,  G06F12/10 ,  G06F3/06

CPC classification number: G06F12/1009 ,  G06F11/1048 ,  G06F12/0246 ,  G06F12/0607 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/65 ,  G06F2212/7201

Abstract: An embodiment includes a system, comprising: an Error Correcting Code (ECC) memory comprising a plurality of memory locations, each memory location corresponding to a device address of the ECC memory; a system management bus (SMB); a baseboard management controller (BMC) coupled to the ECC memory through the SMB; and an operating system comprising a driver module coupled to the BMC through the SMB, the driver module being configured to receive through the Memory device address information associated with the ECC memory and to convert the device address information into physical address information independent of an ECC memory controller.

Abstract translation: 一个实施例包括一种系统，包括：纠错码（ECC）存储器，包括多个存储器位置，每个存储器位置对应于ECC存储器的设备地址; 系统管理总线（SMB）; 通过SMB耦合到ECC存储器的基板管理控制器（BMC）; 以及操作系统，其包括通过所述SMB耦合到所述BMC的驱动器模块，所述驱动器模块被配置为通过所述存储器设备接收与所述ECC存储器相关联的地址信息，并将所述设备地址信息转换为独立于ECC存储器的物理地址信息 控制器。