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公开(公告)号：US20210074720A1
公开(公告)日：2021-03-11
申请号：US16885499
申请日：2020-05-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Younghwan Son , Sanghoon Jeong , Sangjun Hong , Seogoo Kang , Jeehoon Han
IPC: H01L27/11582 , H01L27/1157 , H01L27/11565
Abstract: A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.
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公开(公告)号：US10396088B2
公开(公告)日：2019-08-27
申请号：US15696276
申请日：2017-09-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sohyeon Lee , Sunil Shim , Jaeduk Lee , Jaehoon Jang , Jeehoon Han
IPC: H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L23/52 , H01L23/528 , H01L21/768 , H01L23/522
Abstract: A three-dimensional semiconductor device and a method of manufacturing the same are provided. The three-dimensional semiconductor device includes a stack structure including insulating layers and electrodes that are alternately stacked on a substrate, a horizontal semiconductor pattern between the substrate and the stack structure, vertical semiconductor patterns penetrating the stack structure and connected to the horizontal semiconductor pattern; and a common source plug at a side of the stack structure. The stack structure, the horizontal semiconductor pattern and the common source plug extend in a first direction. The horizontal semiconductor pattern includes a first sidewall extending in the first direction. The first sidewall has protrusions protruding toward the common source plug.
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公开(公告)号：US20250126789A1
公开(公告)日：2025-04-17
申请号：US18661135
申请日：2024-05-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minsoo Shin , Joongshik Shin , Hyeongjin Kim , Jeehoon Han
IPC: H10B43/27 , H01L23/00 , H01L25/065 , H01L25/18 , H10B80/00
Abstract: A three-dimensional semiconductor memory device includes a plurality of peripheral circuit structures on a substrate, a plurality of stacked structures, each the plurality of stacked structures including a plurality of gate electrodes stacked on the plurality of peripheral circuit structure in a first direction perpendicular to a lower surface of the substrate, and the plurality of stacked structure being spaced apart from each other in a second direction parallel to the lower surface of the substrate, a separation structure extending between the plurality of stacked structures in a third direction intersecting the first direction and the second direction, the separation structure including a plurality of support patterns that are spaced apart from each other in the third direction in the separation structure; and an internal insulating layer surrounding a side surface of each of the plurality of support patterns.
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公开(公告)号：US20250107098A1
公开(公告)日：2025-03-27
申请号：US18807157
申请日：2024-08-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kohji Kanamori , Jae-Bok Baek , Donghyuck Jang , Jeehoon Han
Abstract: Disclosed are semiconductor devices and electronic systems. The semiconductor device comprises a semiconductor substrate including first and second cell array regions and a connection region including a lower pad region and an upper pad region, a peripheral circuit structure including peripheral circuits on the semiconductor substrate, and a cell array structure on the peripheral circuit structure and including a first stack structure including first conductive patterns stacked on the peripheral circuit structure and a second stack structure including second conductive patterns stacked on the first stack structure. The first stack structure includes a connection portion that has a uniform thickness on the upper pad region, and first and second stepwise structures that are asymmetric with each other on the lower pad region. The second stack structure includes third and fourth stepwise structures that are symmetric with each other on the connection portion of the first stack structure.
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公开(公告)号：US20250056807A1
公开(公告)日：2025-02-13
申请号：US18790129
申请日：2024-07-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Juseong Min , Jaebok Baek , Taekkyu Yoon , Jeehoon Han
Abstract: A semiconductor device includes a substrate, active regions extending on the substrate in a first direction, the active regions spaced apart from each other in a second direction perpendicular to the first direction, and arranged in a third direction oblique to the first direction and second direction, and gate electrodes disposed on the active regions and including a first edge extending in the second direction, a second edge extending in the first direction, and a corner region defined by the first edge and the second edge, wherein the corner region includes a protrusion having a width narrowing in a direction away from a center of each of the gate electrodes in plan view.
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Patent Agency Ranking
公开(公告)号：US12185548B2
公开(公告)日：2024-12-31
申请号：US17318306
申请日：2021-05-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Giyong Chung , Jaeryong Sim , Kwangyoung Jung , Jeehoon Han
Abstract: A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.
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47.发明授权公开(公告)号：US12185543B2
公开(公告)日：2024-12-31
申请号：US17742043
申请日：2022-05-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sanghun Chun , Kwangyoung Jung , Youngji Noh , Junghwan Park , Jeehoon Han
Abstract: A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.
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公开(公告)号：US20240422983A1
公开(公告)日：2024-12-19
申请号：US18404198
申请日：2024-01-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kohji Kanamori , Seo-Goo Kang , Seunghyun Lee , Jeehoon Han
IPC: H10B43/35 , H01L23/522 , H01L23/528 , H01L25/065 , H10B43/10 , H10B43/27 , H10B43/40 , H10B80/00
Abstract: A semiconductor device and an electronic system are provided. The semiconductor device may include a substrate including a cell array region and a connection region, a stacked structure including conductive patterns stacked on the substrate, an inner supporter that extends into the stacked structure in the connection region, a contact plug that extends into a portion of the stacked structure and electrically connected to one of the conductive patterns and at least partially extends around the inner supporter in plan view, an insulating spacer between the contact plug and the stacked structure and at least partially extends around the contact plug, and outer supporters spaced apart from the contact plug in the connection region and extending into the stacked structure.
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公开(公告)号：US20240292613A1
公开(公告)日：2024-08-29
申请号：US18586624
申请日：2024-02-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kohji Kanamori , Jeehoon Han
CPC classification number: H10B43/20 , H01L29/045 , H01L29/0696
Abstract: A three-dimensional nonvolatile memory device includes: a plurality of insulating layers stacked on a substrate in a vertical direction substantially perpendicular to a surface of the substrate; a plurality of channel layers positioned between the plurality of insulating layers, and elongated in a first horizontal direction that is parallel to the surface of the substrate, wherein the plurality of channel layers includes a first metal element; a diffusion stop layer conformally formed in a trench passing through the plurality of insulating layers and the plurality of channel layers in the vertical direction; and a crystalline semiconductor pattern between each of the plurality of channel layers and the diffusion stop layer, wherein the crystalline semiconductor pattern includes a second metal element, wherein a concentration of the second metal element in the crystalline semiconductor pattern is higher than a concentration of the first metal element in the plurality of channel layers.
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公开(公告)号：US12058866B2
公开(公告)日：2024-08-06
申请号：US17204248
申请日：2021-03-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeryong Sim , Shinhwan Kang , Jeehoon Han
CPC classification number: H10B43/50 , H01L23/481 , H10B43/27
Abstract: A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy vertical structure are contacting the pattern structure, and wherein at least one of the dummy vertical structures extend further into the pattern structure than the memory vertical structure in a downward direction.
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