公开(公告)号：US10248565B2

公开(公告)日：2019-04-02

申请号：US15268791

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F9/45 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0817 ,  G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0831

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing a hybrid input/output (I/O) coherent write request on a computing device, including receiving an I/O coherent write request, generating a first hybrid I/O coherent write request and a second hybrid I/O coherent write request from the I/O coherent write request, sending the first hybrid I/O coherent write request and I/O coherent write data of the I/O coherent write request to a shared memory, and sending the second hybrid I/O coherent write request without the I/O coherent write data of the I/O coherent write request to a coherency domain.

公开(公告)号：US20180081804A1

公开(公告)日：2018-03-22

申请号：US15268768

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/0808 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0877

CPC classification number: G06F12/0808 ,  G06F9/505 ,  G06F9/5083 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0877 ,  G06F12/12 ,  G06F12/128 ,  G06F2209/509 ,  G06F2212/1041 ,  G06F2212/621

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing dynamic input/output (I/O) coherent workload processing on a computing device. Aspect methods may include offloading, by a processing device, a workload to a hardware accelerator for execution using an I/O coherent mode, detecting a dynamic trigger for switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator, and switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator.

公开(公告)号：US09910799B2

公开(公告)日：2018-03-06

申请号：US15089814

申请日：2016-04-04

Applicant: QUALCOMM Incorporated

Inventor： Christophe Avoinne ,  Jason Edward Podaima ,  Manokanthan Somasundaram ,  Bohuslav Rychlik ,  Thomas Zeng ,  Jaya Subramaniam Ganasan ,  Kun Xu

IPC: G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F15/173 ,  G06F9/50 ,  G06F9/54 ,  G06F9/455

CPC classification number: G06F13/28 ,  G06F9/5016 ,  G06F9/5077 ,  G06F9/546 ,  G06F12/08 ,  G06F15/17318 ,  G06F2009/45583 ,  G06F2212/657

Abstract: Aspects include computing devices, apparatus, and methods for accelerating distributive virtual memory (DVM) message processing in a computing device. DVM message interceptors may be positioned in various locations within a DVM network of a computing device so that DVM messages may be intercepted before reaching certain DVM destinations. A DVM message interceptor may receive a broadcast DVM message from first DVM source. The DVM message interceptor may determine whether a preemptive DVM message response should be returned to the DVM source on behalf of the DVM destination. When certain criteria are met, the DVM message interceptor may generate a preemptive DVM message response to the broadcast DVM message, and send the preemptive DVM message response to the DVM source.

公开(公告)号：US09858196B2

公开(公告)日：2018-01-02

申请号：US14462773

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Ali Iranli ,  Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/0886 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0893 ,  G06F12/0886 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by combining the data with padding data of a size of a difference between a size of a cache line and the data. A processor may determine whether the data, uncompressed or compressed, is smaller than a cache line using a size of the data or a compression ratio of the data. The processor may generate the padding data using constant data values or a pattern of data values. The processor may send a write cache memory access request for the combined data to a cache memory controller, which may write the combined data to a cache memory. The cache memory controller may send a write memory access request to a memory controller, which may write the combined data to a memory.

公开(公告)号：US20170286335A1

公开(公告)日：2017-10-05

申请号：US15089814

申请日：2016-04-04

Applicant: QUALCOMM Incorporated

Inventor： Christophe Avoinne ,  Jason Edward Podaima ,  Manokanthan Somasundaram ,  Bohuslav Rychlik ,  Thomas Zeng ,  Jaya Subramaniam Ganasan ,  Kun Xu

IPC: G06F13/28 ,  G06F12/08

CPC classification number: G06F13/28 ,  G06F9/5016 ,  G06F9/5077 ,  G06F9/546 ,  G06F12/08 ,  G06F15/17318 ,  G06F2009/45583 ,  G06F2212/657

Abstract: Aspects include computing devices, apparatus, and methods for accelerating distributive virtual memory (DVM) message processing in a computing device. DVM message interceptors may be positioned in various locations within a DVM network of a computing device so that DVM messages may be intercepted before reaching certain DVM destinations. A DVM message interceptor may receive a broadcast DVM message from first DVM source. The DVM message interceptor may determine whether a preemptive DVM message response should be returned to the DVM source on behalf of the DVM destination. When certain criteria are met, the DVM message interceptor may generate a preemptive DVM message response to the broadcast DVM message, and send the preemptive DVM message response to the DVM source.

公开(公告)号：US20170255497A1

公开(公告)日：2017-09-07

申请号：US15603863

申请日：2017-05-24

Applicant: QUALCOMM Incorporated

Inventor： Mehrdad Mohammad H. RESHADI ,  Babak Salamat ,  Gheorghe c. Cascaval ,  Mark S. Fowler ,  Andrey Ermolinskiy ,  Bohuslav Rychlik

IPC: G06F9/50 ,  G06F3/0481

CPC classification number: G06F9/5061 ,  G06F3/0481

Abstract: Systems and methods enable displaying a graphical representation of system resource usage in a resource utilization map to inform users about system resource utilization by applications and processes running on a computing device. Users may provide inputs to enable the system to adjust resource allocations based on user preferences. This may enable users to improve the overall operational performance of the device consistent with their current personal preferences by identifying applications or processes of most or least interest so the device processor to prioritize system resources accordingly. Some aspects transmit resource allocation data based on such user input to a central server to enable community based resource allocation schemes. Community based resource allocation schemes may be transmitted to computing devices for use as default or preliminary resource allocations for particular applications, websites or device operating states.

公开(公告)号：US09495291B2

公开(公告)日：2016-11-15

申请号：US14251626

申请日：2014-04-13

Applicant: QUALCOMM Incorporated

Inventor： Feng Wang ,  Bohuslav Rychlik ,  Anwar Q. Rohillah

IPC: G06F12/06

CPC classification number: G06F12/0607 ,  G06F2212/1016

Abstract: A method of interleaving a memory by mapping address bits of the memory to a number N of memory channels iteratively in successive rounds, wherein in each round except the last round: selecting a unique subset of address bits, determining a maximum number (L) of unique combinations possible based on the selected subset of address bits, mapping combinations to the N memory channels a maximum number of times (F) possible where each of the N memory channels gets mapped to an equal number of combinations, and if and when a number of combinations remain (K, which is less than N) that cannot be mapped, one to each of the N memory channels, entering a next round. In the last round, mapping remaining most significant address bits, not used in the subsets in prior rounds, to each of the N memory channels.

Abstract translation: 一种通过在连续循环中迭代地将存储器的地址位映射到数量N个存储器通道来交织存储器的方法，其中在除了最后一轮之外的每个循环中：选择唯一的地址位子集，确定最大数目（L） 基于所选择的地址位子集可能的唯一组合，将N个存储器通道中的每一个映射到相等数量的组合的最大次数（F）映射到N个存储器通道，以及如果和何时一个数字 的组合保持（K小于N），N个存储器通道中的每一个输入下一轮。 在最后一轮中，将剩余的最高有效地址位映射到N个存储器通道中的每一个。

公开(公告)号：US09489305B2

公开(公告)日：2016-11-08

申请号：US14571876

申请日：2014-12-16

Applicant: QUALCOMM INCORPORATED

Inventor： George Patsilaras ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  Kris Tiri ,  Jeong-Ho Woo ,  Anwar Rohillah ,  Feng Wang ,  Moinul Khan ,  Subbarao Palacharla

IPC: G06F12/00 ,  G06F12/08 ,  G06F1/32 ,  G06F13/16 ,  G06F9/46

CPC classification number: G06F12/0802 ,  G06F1/3253 ,  G06F9/467 ,  G06F12/0804 ,  G06F12/0835 ,  G06F12/0891 ,  G06F13/16 ,  G06F2212/604 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various embodiments of methods and systems for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”) are disclosed. Because power consumption and bus bandwidth are unnecessarily consumed when ephemeral data is written back to long term memory (such as a double data rate “DDR” memory) from a closely coupled memory component (such as a low level cache “LLC” memory) of a data generating master component, embodiments of the solutions seek to identify write transactions that contain ephemeral data and prevent the ephemeral data from being written to DDR.

Abstract translation: 公开了用于在芯片上的系统（“SoC”）中管理从主组件到长期存储器组件的写事务量的方法和系统的各种实施例。 因为当临时数据从紧密耦合的存储器组件（例如低级缓存“LLC”存储器））写入长期存储器（例如双倍数据速率“DDR”存储器）时，功耗和总线带宽被不必要地消耗 数据生成主组件，解决方案的实施例寻求识别包含短暂数据的写事务，并防止短暂数据被写入DDR。

公开(公告)号：US09465735B2

公开(公告)日：2016-10-11

申请号：US14045784

申请日：2013-10-03

Applicant: Qualcomm Incorporated

Inventor： Bohuslav Rychlik ,  Feng Wang ,  Anwar Rohillah ,  Simon Booth

IPC: G06F12/06

CPC classification number: G06F12/0607

Abstract: Systems and methods for uniformly interleaving memory accesses across physical channels of a memory space with a non-uniform storage capacity across the physical channels are disclosed. An interleaver is arranged in communication with one or more processors and a system memory. The interleaver identifies locations in a memory space supported by the memory channels and is responsive to logic that defines virtual sectors having a desired storage capacity. The interleaver accesses the asymmetric storage capacity uniformly across the virtual sectors in response to requests to access the memory space.

Abstract translation: 公开了跨物理通道具有不均匀存储容量的存储器空间的物理信道的均匀交织的系统和方法。 交织器布置成与一个或多个处理器和系统存储器通信。 交织器识别由存储器通道支持的存储器空间中的位置，并响应于定义具有期望存储容量的虚拟扇区的逻辑。 响应于访问存储器空间的请求，交织器跨虚拟扇区均匀地访问非对称存储容量。

公开(公告)号：US20160291981A1

公开(公告)日：2016-10-06

申请号：US14679408

申请日：2015-04-06

Applicant: QUALCOMM Incorporated

Inventor： Behnam Robatmili ,  Gheorghe Calin Cascaval ,  Michael William Morrow ,  Derek Jay Conrod ,  Bohuslav Rychlik

IPC: G06F9/38

CPC classification number: G06F9/3857 ,  G06F9/30043 ,  G06F9/3832

Abstract: Removing invalid literal load values, and related circuits, methods, and computer-readable media are disclosed. In one aspect, an instruction processing circuit provides a literal load table containing one or more entries comprising an address and a cached literal load value. Upon detecting a literal load instruction in an instruction stream, the instruction processing circuit determines whether the literal load table contains an entry having an address of the literal load instruction. If so, the instruction processing circuit removes the literal load instruction from the instruction stream, and provides the cached literal load value stored in the entry to at least one dependent instruction. The instruction processing circuit further determines whether an invalidity indicator for the literal load table has been received. If so, the instruction processing circuit flushes the literal load table. The invalidity indicator may be generated responsive to modification of a constant table.

Abstract translation: 公开了删除无效文字负载值以及相关电路，方法和计算机可读介质。 在一个方面，指令处理电路提供包含一个或多个条目的文字加载表，该条目包括地址和缓存的字面负载值。 在指令流中检测到文字加载指令时，指令处理电路确定文字加载表是否包含具有文字加载指令地址的条目。 如果是这样，则指令处理电路从指令流中去除文字加载指令，并将存储在该条目中的缓存的文字加载值提供给至少一个从属指令。 指令处理电路还确定是否已经接收到文字负载表的无效指示符。 如果是这样，指令处理电路刷新文字负载表。 可以响应于常数表的修改来生成无效指示符。