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公开(公告)号：US09990291B2
公开(公告)日：2018-06-05
申请号：US14863645
申请日：2015-09-24
Applicant: QUALCOMM Incorporated
Inventor： Hien Minh Le , Thuong Quang Truong , Kun Xu , Jaya Prakash Subramaniam Ganasan , Cesar Aaron Ramirez
IPC: G06F12/08 , G06F12/0831 , G06F13/16 , G06F13/40 , G06F13/42 , G06F12/0815 , G06F9/52
CPC classification number: G06F12/0831 , G06F9/524 , G06F12/0815 , G06F12/0833 , G06F13/16 , G06F13/4027 , G06F13/42 , G06F2212/1008 , G06F2212/621
Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.
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Patent Agency Ranking
公开(公告)号：US20170091098A1
公开(公告)日：2017-03-30
申请号：US14863645
申请日：2015-09-24
Applicant: QUALCOMM Incorporated
Inventor： Hien Minh Le , Thuong Quang Truong , Kun Xu , Jaya Prakash Subramaniam Ganasan , Cesar Aaron Ramirez
CPC classification number: G06F12/0831 , G06F9/524 , G06F12/0815 , G06F12/0833 , G06F13/16 , G06F13/4027 , G06F13/42 , G06F2212/1008 , G06F2212/621
Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.
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公开(公告)号：US09910799B2
公开(公告)日：2018-03-06
申请号：US15089814
申请日：2016-04-04
Applicant: QUALCOMM Incorporated
Inventor： Christophe Avoinne , Jason Edward Podaima , Manokanthan Somasundaram , Bohuslav Rychlik , Thomas Zeng , Jaya Subramaniam Ganasan , Kun Xu
CPC classification number: G06F13/28 , G06F9/5016 , G06F9/5077 , G06F9/546 , G06F12/08 , G06F15/17318 , G06F2009/45583 , G06F2212/657
Abstract: Aspects include computing devices, apparatus, and methods for accelerating distributive virtual memory (DVM) message processing in a computing device. DVM message interceptors may be positioned in various locations within a DVM network of a computing device so that DVM messages may be intercepted before reaching certain DVM destinations. A DVM message interceptor may receive a broadcast DVM message from first DVM source. The DVM message interceptor may determine whether a preemptive DVM message response should be returned to the DVM source on behalf of the DVM destination. When certain criteria are met, the DVM message interceptor may generate a preemptive DVM message response to the broadcast DVM message, and send the preemptive DVM message response to the DVM source.
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公开(公告)号：US20170286335A1
公开(公告)日：2017-10-05
申请号：US15089814
申请日：2016-04-04
Applicant: QUALCOMM Incorporated
Inventor： Christophe Avoinne , Jason Edward Podaima , Manokanthan Somasundaram , Bohuslav Rychlik , Thomas Zeng , Jaya Subramaniam Ganasan , Kun Xu
CPC classification number: G06F13/28 , G06F9/5016 , G06F9/5077 , G06F9/546 , G06F12/08 , G06F15/17318 , G06F2009/45583 , G06F2212/657
Abstract: Aspects include computing devices, apparatus, and methods for accelerating distributive virtual memory (DVM) message processing in a computing device. DVM message interceptors may be positioned in various locations within a DVM network of a computing device so that DVM messages may be intercepted before reaching certain DVM destinations. A DVM message interceptor may receive a broadcast DVM message from first DVM source. The DVM message interceptor may determine whether a preemptive DVM message response should be returned to the DVM source on behalf of the DVM destination. When certain criteria are met, the DVM message interceptor may generate a preemptive DVM message response to the broadcast DVM message, and send the preemptive DVM message response to the DVM source.
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公开(公告)号：US09921962B2
公开(公告)日：2018-03-20
申请号：US14863535
申请日：2015-09-24
Applicant: QUALCOMM Incorporated
Inventor： Kun Xu , Thuong Quang Truong , Jaya Prakash Subramaniam Ganasan , Hien Minh Le , Cesar Aaron Ramirez
IPC: G06F12/00 , G06F13/00 , G06F13/28 , G06F12/0815 , G06F12/0831
CPC classification number: G06F12/0815 , G06F12/0831 , G06F2212/1024 , G06F2212/1028 , G06F2212/621 , Y02D10/13
Abstract: Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.
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公开(公告)号：US20170091095A1
公开(公告)日：2017-03-30
申请号：US14863535
申请日：2015-09-24
Applicant: QUALCOMM Incorporated
Inventor： Kun Xu , Thuong Quang Truong , Jaya Prakash Subramaniam Ganasan , Hien Minh Le , Cesar Aaron Ramirez
IPC: G06F12/08
CPC classification number: G06F12/0815 , G06F12/0831 , G06F2212/1024 , G06F2212/1028 , G06F2212/621 , Y02D10/13
Abstract: Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.
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