公开(公告)号：US20190094939A1

公开(公告)日：2019-03-28

申请号：US15713105

申请日：2017-09-22

Applicant: QUALCOMM Incorporated

Inventor： Hans Yeager ,  Thomas Basnight ,  Zainab Nasreen Zaidi ,  Cesar Aaron Ramirez

IPC: G06F1/32

Abstract: A method and apparatus is disclosed for minimizing power virus in a network on chip. The method includes an operational metric related to a node with at least one threshold, the node configured to manage communication of a first number of outbound transactions; determining, based on the comparison, a second number of outbound transactions from the first number of outbound transactions that are allowed from the node; and communicating the second number of outbound transactions. An apparatus for minimizing power virus in a network on chip is also disclosed.

公开(公告)号：US09990291B2

公开(公告)日：2018-06-05

申请号：US14863645

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Hien Minh Le ,  Thuong Quang Truong ,  Kun Xu ,  Jaya Prakash Subramaniam Ganasan ,  Cesar Aaron Ramirez

IPC: G06F12/08 ,  G06F12/0831 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0815 ,  G06F9/52

CPC classification number: G06F12/0831 ,  G06F9/524 ,  G06F12/0815 ,  G06F12/0833 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/42 ,  G06F2212/1008 ,  G06F2212/621

Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.

公开(公告)号：US20170091098A1

公开(公告)日：2017-03-30

申请号：US14863645

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Hien Minh Le ,  Thuong Quang Truong ,  Kun Xu ,  Jaya Prakash Subramaniam Ganasan ,  Cesar Aaron Ramirez

IPC: G06F12/08 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F12/0831 ,  G06F9/524 ,  G06F12/0815 ,  G06F12/0833 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/42 ,  G06F2212/1008 ,  G06F2212/621

Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.

公开(公告)号：US09921962B2

公开(公告)日：2018-03-20

申请号：US14863535

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Kun Xu ,  Thuong Quang Truong ,  Jaya Prakash Subramaniam Ganasan ,  Hien Minh Le ,  Cesar Aaron Ramirez

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0815 ,  G06F12/0831

CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/621 ,  Y02D10/13

Abstract: Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.

公开(公告)号：US20170091095A1

公开(公告)日：2017-03-30

申请号：US14863535

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Kun Xu ,  Thuong Quang Truong ,  Jaya Prakash Subramaniam Ganasan ,  Hien Minh Le ,  Cesar Aaron Ramirez

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/621 ,  Y02D10/13

Abstract: Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.