公开(公告)号：US20190094939A1

公开(公告)日：2019-03-28

申请号：US15713105

申请日：2017-09-22

Applicant: QUALCOMM Incorporated

Inventor： Hans Yeager ,  Thomas Basnight ,  Zainab Nasreen Zaidi ,  Cesar Aaron Ramirez

IPC: G06F1/32

Abstract: A method and apparatus is disclosed for minimizing power virus in a network on chip. The method includes an operational metric related to a node with at least one threshold, the node configured to manage communication of a first number of outbound transactions; determining, based on the comparison, a second number of outbound transactions from the first number of outbound transactions that are allowed from the node; and communicating the second number of outbound transactions. An apparatus for minimizing power virus in a network on chip is also disclosed.

公开(公告)号：US20190020586A1

公开(公告)日：2019-01-17

申请号：US15649985

申请日：2017-07-14

Applicant: QUALCOMM Incorporated

Inventor： Ravi Karanam ,  Thomas Basnight ,  Zainab Nasreen Zaidi

IPC: H04L12/801 ,  H04L12/725 ,  H04L12/721 ,  H04L12/933 ,  G06F9/52 ,  G06F13/36

Abstract: Selective insertion of a deadlock recovery buffer in a bus interconnect for deadlock recovery is provided. A bus interconnect is provided that includes router nodes configured to receive new bus transaction messages from agent devices. The router nodes route the received bus transaction messages to other destination router nodes in the bus interconnect to be communicated to designated agent devices. To recover from a deadlock condition when buffers of all router nodes are full, thus halting forward progress of bus transaction messages, a deadlock recovery circuit is provided. The deadlock recovery circuit is configured to detect a bus deadlock condition in the bus interconnect. In response, the deadlock recovery circuit is configured to insert a deadlock recovery buffer that has additional buffer entries in the bus interconnect as another router node to allow forward progress of bus transaction messages to continue to recover from the deadlock condition.