公开(公告)号：US10763124B2

公开(公告)日：2020-09-01

申请号：US16194547

申请日：2018-11-19

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Noriyuki Matsubara ,  Shogo Okita ,  Hidehiko Karasaki

IPC: H01L21/20 ,  H01L21/306 ,  G03F7/038 ,  G03F7/40 ,  H01L21/78 ,  H01L29/06 ,  H01L21/311 ,  H01L23/00 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/82 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/308 ,  H01L21/683 ,  H01J37/00

Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of dicing regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a first resin and an organic solvent having a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the dicing regions, plasma-etching the substrate along the dicing regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.

公开(公告)号：US10424488B2

公开(公告)日：2019-09-24

申请号：US16009352

申请日：2018-06-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Atsushi Harikai

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/677 ,  H01L21/78 ,  H01L21/67 ,  H01L21/683 ,  H01L21/687

Abstract: The yield of a product is improved when a substrate held by a conveyance carrier is subjected to a plasma treatment. A method of manufacturing an electronic component includes preparing a substrate which is bonded to a holding sheet of a conveyance carrier, the conveyance carrier including the holding sheet and a frame disposed on an outer peripheral portion of the holding sheet, the substrate having a circuit layer; heating the holding sheet after preparing the substrate; cooling the holding sheet after heating the holding sheet; and plasma etching the substrate to singulate the substrate into the electronic component in a state that the substrate is placed above a stage included in a plasma treatment apparatus and the substrate is in contact with the stage via the holding sheet.

公开(公告)号：US10276423B2

公开(公告)日：2019-04-30

申请号：US15893999

申请日：2018-02-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Koji Tamura ,  Akihiro Itou ,  Atsushi Harikai ,  Noriyuki Matsubara

IPC: H01L21/683 ,  H01L21/78 ,  H01L21/308 ,  H01L21/3065 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor chip includes: preparing a semiconductor wafer; forming a mask on a front surface of the semiconductor wafer so as to cover each of the element regions and to expose the dividing region; exposing the front surface to plasma in a state where a back surface of the semiconductor wafer is held with a dicing tape to dice the semiconductor wafer into a plurality of semiconductor chips by etching the dividing region exposed from the mask up to the back surface while protecting each of the element regions with the mask from plasma; and removing the mask from the front surface together with an adhesive tape by peeling off the adhesive tape after sticking the adhesive tape to the side of the front surface.

公开(公告)号：US10049933B2

公开(公告)日：2018-08-14

申请号：US15594690

申请日：2017-05-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Akihiro Itou ,  Katsumi Takano ,  Mitsuru Hiroshima

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/683 ,  H01L23/00 ,  H01L21/302 ,  H01L21/304

Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface provided with a bump and a second surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of adhering a protection tape having an adhesive layer to the first surface and embedding. The element chip manufacturing method includes a thinning process of grinding the second surface in a state where the protection tape is adhered to the first surface and thinning the substrate, after the bump embedding process, a mask forming process of forming a mask in the second surface and exposes the dividing regions, after the thinning process, a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape.

公开(公告)号：US10037891B2

公开(公告)日：2018-07-31

申请号：US15427561

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo Okita ,  Atsushi Harikai

IPC: H01L21/00 ,  H01L21/3065 ,  H01L21/78 ,  H01L23/544 ,  H01L21/311 ,  H01L21/67 ,  H01L21/683 ,  H01L21/687

CPC classification number: H01L21/3065 ,  H01L21/30655 ,  H01L21/31138 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/6831 ,  H01L21/68742 ,  H01L21/68785 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/5446

Abstract: A manufacturing method of an element chip includes a preparation process of adhering a holding sheet to the first main surface of a substrate so as to prepare the substrate held by the holding sheet, a plasma dicing process of performing plasma etching on the isolation region of the substrate to the first main surface so as to divide the substrate into the plurality of element chips. The plasma dicing process includes a first plasma etching process of performing plasma etching on a the isolation region partially in a thickness direction while a cooling gas is supplied between the stage and the holding sheet, and a second plasma etching process of stopping a supply of the cooling gas after the first plasma etching process, and performing plasma etching on a remaining portion of the isolation region.

公开(公告)号：US09953906B2

公开(公告)日：2018-04-24

申请号：US15408750

申请日：2017-01-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Noriyuki Matsubara

IPC: H01L21/784 ,  H01L23/498 ,  H01L21/3065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/563 ,  H01L21/78 ,  H01L21/784 ,  H01L23/3171 ,  H01L23/3185 ,  H01L24/09 ,  H01L24/89 ,  H01L2224/80801 ,  H01L2224/81 ,  H01L2924/15323

Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by insulating film, the substrate is divided into element chips by exposing the substrate to a first plasma, element chips having first surface, second surface, and side surface are held spaced from each other on carrier, insulating film is in a state of being exposed, recessed portions are formed by retreating insulating film by exposing element chips to second plasma for ashing, and then recessed portions are covered by protection films by third plasma for formation of the protection film, thereby suppressing creep-up of the conductive material to side surface in the mounting step.

公开(公告)号：US09922899B2

公开(公告)日：2018-03-20

申请号：US15408718

申请日：2017-01-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Noriyuki Matsubara ,  Mitsuru Hiroshima ,  Mitsuhiro Okune

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/544 ,  H01L21/3065 ,  H01L21/02 ,  H01L23/29

CPC classification number: H01L23/3178 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31138 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/293 ,  H01L23/3185 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/5446

Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into the element chips by exposing the substrate to first plasma. Therefore, the element chips having a first surface, a second surface, and a side surface on which a plurality of convex portions are formed are held spaced from each other on a carrier. A protection film is formed on the side surface of the element chip by exposing the element chip to second plasma, at least convex portions formed on the side surface are covered by the protection film in the protection film formation, and creep-up of a conductive material to the side surface is suppressed in the mounting step.

公开(公告)号：US09859144B2

公开(公告)日：2018-01-02

申请号：US15258717

申请日：2016-09-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Noriyuki Matsubara

IPC: H01L21/00 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: In a plasma processing process used for a method of manufacturing element chips by which a plurality of element chips are manufactured by dividing a substrate having a plurality of element regions, the substrate is exposed to first plasma, and thereby the substrate is divided into element chips, and the element chips having first surfaces, second surfaces, and side surfaces connecting the first surfaces to the second surfaces are held with an interval between the element chips on the carrier. The element chips are exposed to second plasma which uses a mixed gas of fluorocarbon and helium as a raw material gas, and thereby a protection film covering the side surfaces is formed, and a conductive material is prevented from creeping up to the side surfaces during a mounting process.

公开(公告)号：US09780021B2

公开(公告)日：2017-10-03

申请号：US15408770

申请日：2017-01-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Shogo Okita ,  Noriyuki Matsubara

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3171 ,  H01L24/09 ,  H01L24/89 ,  H01L2224/80801 ,  H01L2924/15323

Abstract: To provide a method of manufacturing an element chip in which creep-up of a conductive material can be suppressed in a mounting step. In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by an insulating film, the substrate is divided into the element chips by exposing the substrate to a first plasma, the element chips having a first surface, a second surface, and a side surface are held spaced from each other on a carrier, and the side surface and the insulating film are in a state of being exposed.

公开(公告)号：US09431263B2

公开(公告)日：2016-08-30

申请号：US14719797

申请日：2015-05-22

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Harikai ,  Noriyuki Matsubara ,  Mitsuru Hiroshima

IPC: H01L21/3065 ,  H01J37/32 ,  C23C16/505 ,  C23C16/458 ,  C23C16/455 ,  H01L21/308 ,  H01L21/67 ,  H01L21/683

CPC classification number: H01L21/3065 ,  C23C16/455 ,  C23C16/458 ,  C23C16/4583 ,  C23C16/4585 ,  C23C16/4586 ,  C23C16/505 ,  H01J37/32082 ,  H01J37/321 ,  H01J37/3244 ,  H01J37/32651 ,  H01J37/32715 ,  H01J37/32724 ,  H01L21/308 ,  H01L21/67069 ,  H01L21/6831 ,  H01L21/6833

Abstract: A plasma processing method to a substrate includes a first step of mounting a transfer carrier holding the substrate on a stage which is cooled and provided within a processing chamber; a second step of relatively moving the stage and a cover provided above the stage to cover a holding sheet and an annular frame of the transfer carrier with the substrate exposed from a window part formed at the cover, a third step of carrying out plasma processing on the substrate, a fourth step of cooling the cover, and a fifth step of unloading the transfer carrier holding the substrate from the processing chamber.

Abstract translation: 对衬底的等离子体处理方法包括：将保持衬底的转印载体安装在冷却并设置在处理室内的台上的第一步骤; 相对移动舞台的第二步骤和设置在舞台上方的盖子覆盖保持片和转印支架的环形框架，其中衬底从形成在盖子上的窗口部分露出，第三步骤对 基板，冷却盖的第四步骤以及从处理室卸载保持基板的转印载体的第五步骤。