公开(公告)号：US07258892B2

公开(公告)日：2007-08-21

申请号：US10733523

申请日：2003-12-10

Applicant: Kevin L. Beaman ,  Trung T. Doan ,  Lyle D. Breiner ,  Ronald A. Weimer ,  Er-Xuan Ping ,  David J. Kubista ,  Cem Basceri ,  Lingyi A. Zheng

Inventor： Kevin L. Beaman ,  Trung T. Doan ,  Lyle D. Breiner ,  Ronald A. Weimer ,  Er-Xuan Ping ,  David J. Kubista ,  Cem Basceri ,  Lingyi A. Zheng

IPC: C23C16/52 ,  B05C11/00 ,  H05B1/02

CPC classification number: C23C16/00 ,  C23C16/46

Abstract: The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.

Abstract translation: 本公开提供了用于控制温度的方法和系统。 该方法在沉积工艺中控制温度，例如通过CVD沉积热反射材料方面具有特别的用途。 一个示例性实施例提供了一种方法，其涉及监测沉积室外的第一温度和沉积室内的第二温度。 通过（a）将控制温度与目标温度进行比较，可以根据斜坡分布来增加沉积室中的内部温度，以及（b）响应于比较的结果，选择性地将热量输送到沉积室。 目标温度可以根据斜坡曲线来确定，但是一个实施例中的控制温度在第一温度和第二温度之间交替。

公开(公告)号：US07081656B2

公开(公告)日：2006-07-25

申请号：US10757252

申请日：2004-01-13

Applicant: Denise M. Eppich ,  Ronald A. Weimer

Inventor： Denise M. Eppich ,  Ronald A. Weimer

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/28194 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28167 ,  H01L21/28202 ,  H01L27/0629 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/90 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 Å (or alternatively comprising a thickness resulting from no more than 70 ALD cycles) is formed between conductively-doped silicon and a dielectric layer. The conductively-doped silicon can be n-type silicon and the dielectric layer can be a high-k dielectric material. The metal-containing material can be formed directly on the dielectric layer, and the conductively-doped silicon can be formed directly on the metal-containing material. The circuit device can be a capacitor construction or a transistor construction. If the circuit device is a transistor construction, such can be incorporated into a CMOS assembly. Various devices of the present invention can be incorporated into memory constructions, and can be incorporated into electronic systems.

Abstract translation: 本发明包括形成电路装置的方法。 在导电掺杂的硅和电介质层之间形成包含不大于（或者包括不超过70个ALD循环的厚度）的厚度的含金属材料。 导电掺杂的硅可以是n型硅，并且介电层可以是高k电介质材料。 含金属材料可以直接形成在电介质层上，并且导电掺杂的硅可以直接形成在含金属的材料上。 电路器件可以是电容器结构或晶体管结构。 如果电路器件是晶体管结构，则可以将其并入CMOS组件中。 本发明的各种装置可以结合到存储器结构中，并且可以并入到电子系统中。

公开(公告)号：US07064052B2

公开(公告)日：2006-06-20

申请号：US10133390

申请日：2002-04-29

Applicant: Ronald A. Weimer ,  Scott J. DeBoer ,  Dan Gealy ,  Husam N. Al-Shareef

Inventor： Ronald A. Weimer ,  Scott J. DeBoer ,  Dan Gealy ,  Husam N. Al-Shareef

IPC: H01L21/3205

CPC classification number: H01L21/3105 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/901

Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

Abstract translation: 制造半导体器件的方法包括沉积电介质膜并使电介质膜在快速热处理室中进行湿氧化。 该技术可以用于例如在集成电路中形成各种元件，包括栅介质膜以及电容元件。 通过RTP工艺提供的紧密温度控制允许快速进行湿氧化，使得氧化物质不会通过电介质膜显着扩散并扩散到下层。 在电容元件的情况下，该技术还可以有助于降低电介质膜的漏电流，而不会显着降低其电容。

公开(公告)号：US06949789B2

公开(公告)日：2005-09-27

申请号：US10013322

申请日：2001-11-13

Applicant: Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

Inventor： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/788

CPC classification number: H01L29/517 ,  H01L21/28273 ,  H01L29/511

Abstract: The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. By exposing the etched gate stack to elevated temperatures and a dilute steam ambient, additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. In the preferred embodiment, the interface is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability due to enhanced charge transfer along grain boundaries. At the same time, oxide in an upper storage dielectric layer (oxide-nitride-oxide or ONO) is enhanced in the dilute steam oxidation. Thermal budget can be radically conserved by growing thin oxide layers on either side of a nitride layer prior to etching, and enhancing the oxide layers by dilute steam oxidation through the exposed sidewall after etching. The thin oxide layers, like the initial tunnel oxide, serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

Abstract translation: 本发明提供一种闪速存储器集成电路及其制造方法。 该方法包括蚀刻包括与硅层直接接触的初始氧化物层的栅极堆叠，在其之间限定氧化物 - 硅界面。 通过将蚀刻的栅极堆叠暴露于升高的温度和稀释的蒸气环境，沿着氧化物 - 硅界面基本均匀地形成附加的氧化物材料。 因此在界面处的多晶硅晶界被蚀刻后钝化。 在优选实施例中，在隧道氧化物和浮动栅极之间形成界面，并且由于沿着晶界的增强的电荷转移而使晶界钝化从而减小了擦除可变性。 同时，在稀释蒸汽氧化中，上部存储介质层（氧化物 - 氧化物 - 氧化物或ONO）中的氧化物被增强。 通过在蚀刻之前在氮化物层的任一侧上生长薄的氧化物层，并且通过在蚀刻后通过暴露的侧壁进行稀释的蒸汽氧化来增强氧化物层，从而可以完全保守热预算。 薄氧化物层，如初始隧道氧化物，用作扩散路径，以增强OH物质穿过被氧化的掩埋界面的均匀分布。

公开(公告)号：US06882031B2

公开(公告)日：2005-04-19

申请号：US10012665

申请日：2001-10-30

Applicant: Ronald A. Weimer ,  Fernando Gonzalez

Inventor： Ronald A. Weimer ,  Fernando Gonzalez

IPC: H01L21/28 ,  H01L21/30 ,  H01L21/318 ,  H01L23/31 ,  H01L29/51 ,  H01L29/06 ,  H01L29/94

CPC classification number: H01L21/28185 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/3003 ,  H01L21/3185 ,  H01L23/3171 ,  H01L29/513 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A passivation method includes disassociating ammonia so as to expose at least interfaces between silicon-containing and passivation structures to at least hydrogen species derived from the ammonia and forming an encapsulant layer that is positioned so as to substantially contain the hydrogen species in the presence of the interfaces. The hydrogen passivation reduces a concentration of dangling silicon bonds at the interfaces by as much as about two orders of magnitude or greater. The encapsulant layer, which may include silicon nitride, prevents hydrogen species from escaping therethrough as high temperature processes are subsequently conducted. Once high temperature processes have been completed, portions of the encapsulant layer may be removed, as needed, to provide access to features of the semiconductor device structure that underlie the encapsulant layer. Semiconductor device structures that have been passivated in such a manner are also disclosed.

Abstract translation: 钝化方法包括使氨分解，以至少将含硅和钝化结构之间的界面暴露于源自氨的至少氢物质，并形成一个密封剂层，该密封剂层被定位成在存在下基本上含有氢物质 接口 氢钝化将界面处的悬挂硅键的浓度降低了大约两个数量级或更多。 可以包括氮化硅的密封剂层通过随后进行高温处理来防止氢物质逸出。 一旦高温处理已经完成，根据需要可以去除部分密封剂层，以提供对构成密封剂层的半导体器件结构的特征的访问。 已经以这种方式钝化的半导体器件结构也被公开。

公开(公告)号：US06784124B2

公开(公告)日：2004-08-31

申请号：US10379884

申请日：2003-03-05

Applicant: Ronald A. Weimer ,  Don Carl Powell

Inventor： Ronald A. Weimer ,  Don Carl Powell

IPC: H01L2100

CPC classification number: H01L28/91 ,  H01L21/3105 ,  Y10S438/958

Abstract: A method for conditioning or repairing a dielectric structure of a semiconductor device structure with selectivity over an adjacent conductive or semiconductive structure of the semiconductor device structure, such as a capacitor dielectric and an adjacent bottom electrode of the capacitor. The method includes exposing the dielectric structure and at least an adjacent surface of the conductive or semiconductive structure to an oxidizing atmosphere that includes at least one oxidant and hydrogen species. The at least one hydrogen species adsorbs to a surface of the conductive or semiconductive structure so as to substantially prevent passage of the at least one oxidant into or through the conductive or semiconductive structure. The oxidant oxidizes or repairs voids or other defects that may be present in the dielectric structure. Semiconductor device structures fabricated by employing the method are also disclosed.

Abstract translation: 用于调节或修复半导体器件结构的电介质结构的方法，其具有对半导体器件结构的相邻导电或半导体结构（诸如电容器电介质和电容器的相邻底部电极）的相邻导电或半导体结构的选择性。 该方法包括将导电或半导体结构的介电结构和至少相邻表面暴露于包括至少一种氧化剂和氢物质的氧化气氛。 所述至少一种氢物质吸附到导电或半导体结构的表面，以便基本上防止至少一种氧化剂进入导电或半导体结构中。 氧化剂氧化或修复可能存在于电介质结构中的空隙或其它缺陷。 还公开了通过采用该方法制造的半导体器件结构。

公开(公告)号：US06762451B2

公开(公告)日：2004-07-13

申请号：US10212937

申请日：2002-08-05

Applicant: Ronald A. Weimer

Inventor： Ronald A. Weimer

IPC: H01L29788

CPC classification number: B82Y10/00 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/28273 ,  H01L21/3205 ,  H01L29/42324 ,  H01L29/4916

Abstract: The present invention provides a method for improving the erase speed and the uniformity of erase characteristics in erasable programmable read-only memories. This result is achieved by forming polycrystalline floating gate layers with optimized grain size on a tunnel dielectric layer. Nucleation sites are formed by exposing the tunnel dielectric layer to a first set of conditions including a first temperature and a first atmosphere selected to optimize nucleation site size and distribution density across the tunnel dielectric layer. A polycrystalline floating gate layer is formed on top of the nucleation sites by exposing the nucleation sites to a second set of conditions including a second temperature and a second atmosphere selected to optimize polycrystalline grain size and distribution density across the polycrystalline floating gate layer.

公开(公告)号：US06734531B2

公开(公告)日：2004-05-11

申请号：US10391266

申请日：2003-03-18

Applicant: Ronald A. Weimer ,  Don Carl Powell

Inventor： Ronald A. Weimer ,  Don Carl Powell

IPC: H01L2328

CPC classification number: H01L28/91 ,  H01L21/3105 ,  Y10S438/958

Abstract: A method for conditioning or repairing a dielectric structure of a semiconductor device structure with selectivity over an adjacent conductive or semiconductive structure of the semiconductor device structure, such as a capacitor dielectric and an adjacent bottom electrode of the capacitor. The method includes exposing the dielectric structure and at least an adjacent surface of the conductive or semiconductive structure to an oxidizing atmosphere that includes at least one oxidant and hydrogen species. The at least one hydrogen species adsorbs to a surface of the conductive or semiconductive structure so as to substantially prevent passage of the at least one oxidant into or through the conductive or semiconductive structure. The oxidant oxidizes or repairs voids or other defects that may be present in the dielectric structure. Semiconductor device structures fabricated by employing the method are also disclosed.

Abstract translation: 用于调节或修复半导体器件结构的电介质结构的方法，其具有对半导体器件结构的相邻导电或半导体结构（诸如电容器电介质和电容器的相邻底部电极）的相邻导电或半导体结构的选择性。 该方法包括将导电或半导体结构的介电结构和至少相邻表面暴露于包括至少一种氧化剂和氢物质的氧化气氛。 所述至少一种氢物质吸附到导电或半导体结构的表面，以便基本上防止至少一种氧化剂进入导电或半导体结构中。 氧化剂氧化或修复可能存在于电介质结构中的空隙或其它缺陷。 还公开了通过采用该方法制造的半导体器件结构。

公开(公告)号：US06576979B2

公开(公告)日：2003-06-10

申请号：US10062123

申请日：2002-01-31

Applicant: Ronald A. Weimer ,  Don Carl Powell

Inventor： Ronald A. Weimer ,  Don Carl Powell

IPC: H01L2358

CPC classification number: H01L28/91 ,  H01L21/3105 ,  Y10S438/958

Abstract: A method for conditioning or repairing a dielectric structure of a semiconductor device structure with selectivity over an adjacent conductive or semiconductive structure of the semiconductor device structure, such as a capacitor dielectric and an adjacent bottom electrode of the capacitor. The method includes exposing the dielectric structure and at least an adjacent surface of the conductive or semiconductive structure to an oxidizing atmosphere that includes at least one oxidant and hydrogen species. The at least one hydrogen species adsorbs to a surface of the conductive or semiconductive structure so as to substantially prevent passage of the at least one oxidant into or through the conductive or semiconductive structure. The oxidant oxidizes or repairs voids or other defects that may be present in the dielectric structure. Semiconductor device structures fabricated by employing the method are also disclosed.

公开(公告)号：US06410968B1

公开(公告)日：2002-06-25

申请号：US09653639

申请日：2000-08-31

Applicant: Don Carl Powell ,  Garry Anthony Mercaldi ,  Ronald A. Weimer

Inventor： Don Carl Powell ,  Garry Anthony Mercaldi ,  Ronald A. Weimer

IPC: H01L31119

CPC classification number: H01L29/513 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02222 ,  H01L21/02263 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/28035 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3125 ,  H01L21/3143 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/3185 ,  H01L28/57 ,  H01L29/518 ,  H01L2924/19041

Abstract: Methods and devices are disclosed utilizing a silicon-containing barrier layer. A method of forming a barrier layer on a semiconductor device is disclosed. A semiconductor device is provided. A silicon-containing material is deposited on the semiconductor device. The silicon-containing material is processed in a reactive ambient. The barrier layer can be made primarily oxide, primarily nitride or both by the reactive ambient selected. A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate oxide, a silicon-containing barrier layer and a gate electrode. The gate oxide is formed over the substrate. The silicon-containing barrier layer is formed over the gate oxide by causing silicon atoms of a precursor layer react with a reactive agent. The gate electrode is formed over the silicon-containing barrier layer. Other embodiments utilizing a barrier layer are disclosed.

Abstract translation: 公开了利用含硅阻挡层的方法和装置。 公开了一种在半导体器件上形成阻挡层的方法。 提供半导体器件。 含硅材料沉积在半导体器件上。 含硅材料在反应性环境中进行处理。 阻挡层可以主要由所选择的反应性环境制成主要是氧化物，主要是氮化物或二者。 公开了一种半导体器件。 半导体器件包括衬底，栅极氧化物，含硅势垒层和栅电极。 栅极氧化物形成在衬底上。 通过使前体层的硅原子与反应剂反应，在栅极氧化物上形成含硅势垒层。 栅电极形成在含硅阻挡层的上方。 公开了利用阻挡层的其它实施例。