公开(公告)号：US07262647B2

公开(公告)日：2007-08-28

申请号：US11307803

申请日：2006-02-23

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/12

Abstract: A delay locked loop circuit and signal delay locking method are provided. First, the start-up circuit minimizes the delay time between an output signal and a reference signal during an initial period. Secondly, the phase correction circuit increases the delay time during an correction period. The present invention ensures that the phase difference between the output signal and the reference signal is correctly detected by the delay locked loop circuit, so that harmonic lock and phase ambiguity can be avoided.

Abstract translation: 提供了延迟锁定环路和信号延迟锁定方法。 首先，启动电路在初始时段期间使输出信号和参考信号之间的延迟时间最小化。 其次，相位校正电路在校正期间增加延迟时间。 本发明确保了延迟锁定环电路正确地检测出输出信号和参考信号之间的相位差，从而可以避免谐波锁定和相位模糊。

公开(公告)号：US07068201B1

公开(公告)日：2006-06-27

申请号：US10907861

申请日：2005-04-19

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H03M1/66

CPC classification number: H03M1/0602 ,  H03M1/682 ,  H03M1/747

Abstract: A digital-to-analog converter (DAC) is disclosed, which provides different bias voltages to the most significant bits (MSBs) and the least significant bits (LSBs) of the digital signal. These two bias voltages can be adjusted according to the match among the current source cells, and maintain a particular proportional relationship. The DAC further includes a bias converter for receiving the first bias voltage, and adjusting the second bias voltage according to the match among the current source cells.

Abstract translation: 公开了一种数模转换器（DAC），其向数字信号的最高有效位（MSB）和最低有效位（LSB）提供不同的偏置电压。 这两个偏置电压可以根据电流源单元之间的匹配进行调整，并保持特定的比例关系。 DAC还包括用于接收第一偏置电压的偏置转换器，以及根据电流源单元之间的匹配来调整第二偏置电压。

公开(公告)号：US20060045225A1

公开(公告)日：2006-03-02

申请号：US10923670

申请日：2004-08-24

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H04L7/00

CPC classification number: H03M1/1255

Abstract: An automatic clock generation system is used for automatically outputting a sampling signal and a holding signal to an analog front end circuit and for sampling the analog signal. The clock generation system comprises a clock generator generating a plurality of clock signals and a comparing module. According to the plurality of clock signals, the comparing module compares the analog signal with a first reference signal and outputs a first comparison signal. The comparing module further compares the digital signal outputted by the analog front end circuit with a second reference signal and outputs a second comparison signal. The clock generator selectively outputs a first clock signal, corresponding to the first comparison signal, of the plurality of clock signals as the sampling signal when the first comparison signal received by the clock generator is at a high state. The clock generator further selectively outputs a second clock signal, corresponding to the second comparison signal, of the plurality of clock signals as the holding signal when the second comparison signal received by the clock generator is at the high state.

公开(公告)号：US20050007461A1

公开(公告)日：2005-01-13

申请号：US10617388

申请日：2003-07-11

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H04N5/228 ,  H04N5/367 ,  H04N5/378 ,  H04N9/04

CPC classification number: H04N5/378 ,  H04N5/3575 ,  H04N5/361

Abstract: The present invention is a correction system applying in an analog front end(AFE). The correction system comprises a correction module, a first digital to analog converter(DAC1) and a second digital to analog converter(DAC2). The correction is used to generate a gain error correction and black pixel signal error correction when the black pixel signal is inputted into the AFE. The correction module corrects the digital output signals generated by the AFE according to the gain error correction. The correction module input the black pixel signal error correction to the DAC1 to generate a first analog correction signal to correct the signal inputted into the AFE. The present invention effectively corrects the signal error generated by the AFE to make the AFE output the corrected digital output signal.

Abstract translation: 本发明是应用于模拟前端（AFE）的校正系统。 校正系统包括校正模块，第一数模转换器（DAC1）和第二数模转换器（DAC2）。 当黑色像素信号被输入到AFE中时，校正用于产生增益误差校正和黑色像素信号纠错。 校正模块根据增益误差校正校正由AFE产生的数字输出信号。 校正模块将黑色像素信号纠错输入到DAC1，以产生第一模拟校正信号，以校正输入到AFE中的信号。 本发明有效地校正由AFE产生的信号误差，使AFE输出校正的数字输出信号。

公开(公告)号：US06825790B2

公开(公告)日：2004-11-30

申请号：US10234469

申请日：2002-09-05

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H03M138

CPC classification number: H03M1/164 ,  H03M1/40

Abstract: This present invention is directed to a stage circuit for a pipelined analog-to-digital converter. The stage circuit includes an amplifier, a comparator, a first compensator and a second compensator, and three modes are developed for the stage circuit in signal processing: a sampling mode, a first amplifying mode and a second amplifying mode. In the sampling mode, the amplifier is inputted with an analog input signal; the comparator compares the analog input signal with a reference signal, and then generates a first digital output code. In the first amplifying mode, the first compensator selectively adds a first compensation value to the analog input signal according to the first digital output code, and then generates a first input signal; the amplifier amplifies the first input signal and then generates a first output signal; the comparator compares the first output signal with the reference signal and then generates a second digital output signal. In the second amplifying mode, the first compensator selectively adds a second compensation value to the analog input signal according to the first digital output code and the second digital output code, and then generates a second input signal; the amplifier amplifies the second input signal and then generates a second output signal; the second compensator selectively chooses a third compensation value according to the first digital output code and the second digital output code, and the third compensation value is amplified and added to the second output signal to generate an analog output signal which sends to the next stage circuit.

Abstract translation: 本发明涉及一种用于流水线模数转换器的级电路。 舞台电路包括放大器，比较器，第一补偿器和第二补偿器，并且在信号处理中为舞台电路开发三种模式：采样模式，第一放大模式和第二放大模式。 在采样模式下，放大器输入模拟输入信号; 比较器将模拟输入信号与参考信号进行比较，然后生成第一数字输出代码。 在第一放大模式中，第一补偿器根据第一数字输出码向模拟输入信号选择性地添加第一补偿值，然后产生第一输入信号; 放大器放大第一输入信号，然后产生第一输出信号; 比较器将第一输出信号与参考信号进行比较，然后产生第二数字输出信号。 在第二放大模式中，第一补偿器根据第一数字输出代码和第二数字输出代码选择性地向模拟输入信号添加第二补偿值，然后产生第二输入信号; 放大器放大第二输入信号，然后产生第二输出信号; 第二补偿器根据第一数字输出码和第二数字输出码有选择地选择第三补偿值，并且第三补偿值被放大并相加到第二输出信号，以产生发送到下一级电路的模拟输出信号 。

公开(公告)号：US06714152B1

公开(公告)日：2004-03-30

申请号：US10369642

申请日：2003-02-21

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H03M134

CPC classification number: H03M1/145 ,  H03M1/44

Abstract: The present invention is a pipelined analog-to-digital converter (Pipelined ADC) for converting a first analog signal to a digital data. The converter comprises at least one first stage circuit, at least one second stage circuit, a third stage circuit, and a code adder. Each of the first stage circuits has a first converting rate for converting a first analog signal to at least one digital code and generating a second analog signal. The second stage circuits are serially connected after the first stage circuit. Each of the second stage circuits has a second converting rate which is higher than the first converting rate for converting the second analog signal to at least two digital codes and generating a third analog signal. The third stage circuit serially connected after the second stage circuits is used for converting the third analog signal to at least one digital code. The code adder is used for combining the digital codes to generate the digital data. Thus, the later half stage circuits of the Pipelined ADC has a higher converting rate, so the converter of the present invention can reduce the number of the stage circuits needed and further reduces the area of the converter.

Abstract translation: 本发明是用于将第一模拟信号转换为数字数据的流水线模数转换器（流水线ADC）。 转换器包括至少一个第一级电路，至少一个第二级电路，第三级电路和代码加法器。 每个第一级电路具有用于将第一模拟信号转换为至少一个数字码并产生第二模拟信号的第一转换速率。 第二级电路在第一级电路之后串联连接。 每个第二级电路具有比用于将第二模拟信号转换成至少两个数字代码并产生第三模拟信号的第一转换速率的第二转换速率。 在第二级电路之后串行连接的第三级电路用于将第三模拟信号转换为至少一个数字代码。 代码加法器用于组合数字代码以生成数字数据。 因此，流水线ADC的后半部电路具有较高的转换速率，因此本发明的转换器可以减少所需的级电路的数量并进一步减小转换器的面积。

公开(公告)号：US06552433B1

公开(公告)日：2003-04-22

申请号：US09858529

申请日：2001-05-17

Applicant: Kuo-Yu Chou ,  Tong-Chern Ong

Inventor： Kuo-Yu Chou ,  Tong-Chern Ong

IPC: H01L2348

CPC classification number: H01L24/05 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/05042 ,  H01L2924/14

Abstract: A vertical structure and a method of forming a vertical structure are disclosed. A partially processed semiconductor wafer is provided having all devise levels completed, including a topmost interlevel dielectric layer through which metallic vias are formed for electrical connection. A first metal level is formed. An IMD level is then formed by forming a blanket dielectric layer over the first metal level, patterning and etching the dielectric layer to form arrays of trenches passing through the dielectric layer, filling the trenches with a conducting material, and performing CMP. A number of metal level, IMD level pairs are formed, where the number could be zero. Bonding metal patterns are deposited, wires are bonded onto the bonding metal patterns and a passivation layer is formed.

Abstract translation: 公开了垂直结构和形成垂直结构的方法。 提供了部分处理的半导体晶片，其具有完成的所有设计水平，包括最顶层的层间电介质层，通过金属通孔形成电气连接。 形成第一金属层。 然后通过在第一金属层上形成覆盖介电层形成IMD电平，对介电层进行构图和蚀刻以形成通过介电层的沟槽阵列，用导电材料填充沟槽，并执行CMP。 形成了多个金属级，IMD级对，其中数字可以为零。 结合金属图案被沉积，导线被接合到接合金属图案上并形成钝化层。

公开(公告)号：US06437396B1

公开(公告)日：2002-08-20

申请号：US09197064

申请日：1998-11-20

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H01L29788

CPC classification number: G11C11/56 ,  H01L21/28273 ,  H01L29/7887 ,  H01L29/7923

Abstract: A structure and a process of a nonvolatile memory are provided. By forming a oxide/nitride/oxide (ONO) layer in a floating gate thin oxide (FLOTOX) memory, the same data can be programmed in one nonvolatile memory to guarantee the reliability but without using two nonvolatile memories. Besides, people can program different data separately to achieve the purpose of multi-state memory.

Abstract translation: 提供非易失性存储器的结构和处理。 通过在浮栅薄氧化物（FLOTOX）存储器中形成氧化物/氮化物/氧化物（ONO）层，可以将相同的数据编程在一个非易失性存储器中，以保证可靠性，但不使用两个非易失性存储器。 此外，人们可以分别编写不同的数据，以达到多状态存储器的目的。

公开(公告)号：US06417553B1

公开(公告)日：2002-07-09

申请号：US09682482

申请日：2001-09-07

Applicant: Kuo-Yu Chou ,  Chien-Shan Chiang ,  Lo-Chun Ho ,  Chih-Hsueh Hsu

Inventor： Kuo-Yu Chou ,  Chien-Shan Chiang ,  Lo-Chun Ho ,  Chih-Hsueh Hsu

IPC: H01L3104

CPC classification number: H01L27/144 ,  H01L31/1136

Abstract: A semiconductor wafer includes a plurality of sensors. Each of the sensors has a field oxide transistor, and a detecting circuit electrically connected to the field oxide transistor for detecting if the field oxide transistor is switched on or off and generating corresponding detecting signals. The field oxide of a different field oxide transistor has a different thickness. Each field oxide transistor is coupled to a corresponding detecting circuit for detecting radiation impinging on the semiconductor wafer.

Abstract translation: 半导体晶片包括多个传感器。 每个传感器具有场氧化物晶体管，以及电连接到场氧化物晶体管的检测电路，用于检测场氧化物晶体管是接通还是断开，并产生相应的检测信号。 不同场氧化物晶体管的场氧化物具有不同的厚度。 每个场氧化物晶体管耦合到相应的检测电路，用于检测照射在半导体晶片上的辐射。

公开(公告)号：US6015728A

公开(公告)日：2000-01-18

申请号：US55580

申请日：1998-04-06

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H01L21/02 ,  H01L21/8244 ,  H01L27/11

CPC classification number: H01L28/20 ,  H01L27/11 ,  H01L27/1112

Abstract: A method for fabricating a static random access memory polyload resistor comprising the steps of first providing a semiconductor substrate having a transistor formed thereon, wherein the transistor includes a gate, a source region and a gate region. Thereafter, a dielectric layer is formed over the substrate, and then photolithographic and etching processes are used to remove a portion of the dielectric layer forming a plurality of vias. Next, a polysilicon layer is formed over the substrate, and then photolithographic and etching processes are again used to pattern the polysilicon layer. Then, ions are doped to form a doped polysilicon layer. In the subsequent step, an anti-oxidation layer is formed over the substrate. Then, photolithographic and etching processes are again used to remove a portion of the polysilicon layer and the anti-oxidation layer forming interconnect regions and load resistor regions. Finally, a thermal oxidation is carried out followed by the removal of the anti-oxidation layer.

Abstract translation: 一种用于制造静态随机存取存储器多负载电阻器的方法，包括以下步骤：首先提供其上形成有晶体管的半导体衬底，其中所述晶体管包括栅极，源极区域和栅极区域。 此后，在衬底上形成电介质层，然后使用光刻和蚀刻工艺去除形成多个通孔的电介质层的一部分。 接下来，在衬底上形成多晶硅层，然后再次使用光刻和蚀刻工艺来对多晶硅层进行图案化。 然后，掺杂离子以形成掺杂的多晶硅层。 在随后的步骤中，在衬底上形成抗氧化层。 然后，再次使用光刻和蚀刻工艺去除多晶硅层的一部分和形成抗氧化层的互连区域和负载电阻器区域。 最后，进行热氧化，然后除去抗氧化层。