公开(公告)号：US11538808B2

公开(公告)日：2022-12-27

申请号：US16124877

申请日：2018-09-07

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Aaron D. Lilak ,  Abhishek A. Sharma ,  Van H. Le ,  Seung Hoon Sung ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L27/12 ,  H01L21/00 ,  H01L27/108 ,  H01L21/822 ,  H01L23/528 ,  H01L49/02 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

Abstract: Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.

公开(公告)号：US11417775B2

公开(公告)日：2022-08-16

申请号：US16043593

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Shriram Shivaraman ,  Van H. Le ,  Abhishek A. Sharma ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Miriam R. Reshotko ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/768 ,  H01L23/00

Abstract: Disclosed herein are transistor gate-channel arrangements that may be implemented in nanowire thin film transistors (TFTs) with textured semiconductors, and related methods and devices. An example transistor gate-channel arrangement may include a substrate, a channel material that includes a textured thin film semiconductor material shaped as a nanowire, a gate dielectric that at least partially wraps around the nanowire, and a gate electrode material that wraps around the gate dielectric. Implementing textured thin film semiconductor channel materials shaped as a nanowire and having a gate stack of a gate dielectric and a gate electrode material wrapping around the nanowire advantageously allows realizing gate all-around or bottom-gate transistor architectures for TFTs with textured semiconductor channel materials.

公开(公告)号：US20210193814A1

公开(公告)日：2021-06-24

申请号：US16075953

申请日：2016-03-04

Applicant: Intel Corporation

Inventor： Gilbert W. Dewey ,  Rafael Rios ,  Van H. Le ,  Jack T. Kavalieros

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/267 ,  H01L29/417 ,  H01L21/02 ,  H01L21/465 ,  H01L29/66

Abstract: FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.

公开(公告)号：US20210074825A1

公开(公告)日：2021-03-11

申请号：US16642254

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Van H. Le ,  Gilbert W. Dewey ,  Willy Rachmady

IPC: H01L29/47 ,  H01L27/24 ,  H01L27/22 ,  H01L29/861 ,  H01L29/872

Abstract: Disclosed herein are selector devices, and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, a selector material between the first electrode and the second electrode, and a getter layer between the first electrode and the selector material. The first electrode may include a material having a work function that is less than 4.5 electron volts.

公开(公告)号：US10811461B2

公开(公告)日：2020-10-20

申请号：US16461334

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Van H. Le ,  Gilbert W. Dewey

IPC: H01L27/24 ,  H01L21/8238 ,  H01L25/065 ,  H01L27/092

Abstract: Substrates, assemblies, and techniques for a transmission gate that includes an n-type back end transistor and a p-type back end transistor in parallel with the n-type back end transistor. The transmission gate can be on a non-silicon substrate and include a second gate, a p-type semiconducting layer over the second gate, an n-type semiconducting layer over the p-type semiconducting layer, a bit line over the n-type semiconducting layer, a first gate over the n-type semiconducting layer, and a source line over the n-type semiconducting layer. The transmission gate may be coupled to a memory element.

公开(公告)号：US20200295127A1

公开(公告)日：2020-09-17

申请号：US16351921

申请日：2019-03-13

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron D. Lilak ,  Anh Phan ,  Cheng-Ying Huang ,  Gilbert W. Dewey ,  Patrick Morrow ,  Rishabh Mehandru ,  Roza Kotlyar ,  Sean T. Ma ,  Willy Rachmady

IPC: H01L29/04 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L25/11 ,  H01L23/00 ,  H01L23/522 ,  H01L29/16 ,  H01L29/20 ,  H01L21/8238 ,  H01L29/66

Abstract: Disclosed herein are stacked transistors with different crystal orientations in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein the channel materials in at least some of the strata have different crystal orientations.

公开(公告)号：US20200294939A1

公开(公告)日：2020-09-17

申请号：US16394905

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Gilbert W. Dewey ,  Hyung-Jin Lee

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L21/48

Abstract: Embodiments may relate to a semiconductor package that includes a die and a package substrate. The package substrate may include one or more cavities that go through the package substrate from a first side of the package substrate that faces the die to a second side of the package substrate opposite the first side. The semiconductor package may further include a waveguide communicatively coupled with the die. The waveguide may extend through one of the one or more cavities such that the waveguide protrudes from the second side of the package substrate. Other embodiments may be described or claimed.