公开(公告)号：US11543793B2

公开(公告)日：2023-01-03

申请号：US16691731

申请日：2019-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Richard C. Johnson ,  Hao Tang ,  Yongan Xu

IPC: G05B19/402 ,  G03F7/30 ,  G03F7/20 ,  B05D1/00

Abstract: Embodiments of the invention include methods and structures for controlling developer critical dimension (DCD) variations across a wafer surface. Aspects of the invention include an apparatus having developer tubing and an internal cam. The internal cam is coupled to a fixed axis. A flexible divider is positioned between the developer tubing and the internal cam. The flexible divider is coupled to the internal cam such that rotation of the internal cam about the fixed axis is operable to change an inner diameter of the developer tubing.

公开(公告)号：US11022887B2

公开(公告)日：2021-06-01

申请号：US16675276

申请日：2019-11-06

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Jing Guo ,  Ekmini A. De Silva ,  Oleg Gluschenkov

IPC: G03F7/20 ,  H01L21/027 ,  G03F7/075 ,  G03F7/085 ,  G03F7/09

Abstract: An EUV lithographic structure and methods according to embodiments of the invention includes an EUV photosensitive resist layer disposed directly on an oxide hardmask layer, wherein the oxide hardmask layer is doped with dopant ions to form a doped oxide hardmask layer so as to improve adhesion between the EUV lithographic structure and the oxide hardmask. The EUV lithographic structure is free of a separate adhesion layer.

公开(公告)号：US10915690B2

公开(公告)日：2021-02-09

申请号：US16383326

申请日：2019-04-12

Applicant: International Business Machines Corporation

Inventor： Dongbing Shao ,  Yongan Xu ,  Shyng-Tsong Chen ,  Zheng Xu

IPC: G06F30/30 ,  G06F30/398

Abstract: Methods and systems for performing an electronic design. A layout of a via of an electronic design is obtained and a determination is made if the layout of the via satisfies one or more retargeting conditions, at least one of the retargeting conditions being that a first edge of a metal line is within a specified distance from a first edge of the via and a second edge of the metal line is within the specified distance from a second edge of the via, the first edge of the metal line being parallel to the first edge of the via and the second edge of the metal line being parallel to the second edge of the via; and reducing a resistance of the via by the layout of the via is retargeted in response to the retargeting conditions being satisfied.

公开(公告)号：US10915085B2

公开(公告)日：2021-02-09

申请号：US15789067

申请日：2017-10-20

Applicant: International Business Machines Corporation

Inventor： Richard C. Johnson ,  Hao Tang ,  Yongan Xu

IPC: G03F7/30 ,  G05B19/402 ,  G03F7/20 ,  B05D1/00

Abstract: Embodiments of the invention include methods and structures for controlling developer critical dimension (DCD) variations across a wafer surface. Aspects of the invention include an apparatus having developer tubing and an internal cam. The internal cam is coupled to a fixed axis. A flexible divider is positioned between the developer tubing and the internal cam. The flexible divider is coupled to the internal cam such that rotation of the internal cam about the fixed axis is operable to change an inner diameter of the developer tubing.

公开(公告)号：US20200066575A1

公开(公告)日：2020-02-27

申请号：US16112286

申请日：2018-08-24

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Yongan Xu ,  Muthumanickam Sankarapandian

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/033 ,  H01L21/311 ,  H01L21/02

Abstract: Techniques for single trench damascene interconnect formation using TiN HMO are provided. In one aspect, a method for forming interconnects on a substrate includes: forming an underlayer on the substrate; forming a hardmask on the underlayer; patterning trenches in the hardmask that extend down to the underlayer; forming the interconnects in the trenches; removing the hardmask; and burying the interconnects in an ILD. The trenches can be patterned in the hardmask using a process such as sidewall image transfer. An interconnect structure is also provided.

公开(公告)号：US20190391481A1

公开(公告)日：2019-12-26

申请号：US16015994

申请日：2018-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yongan Xu ,  Zhenxing Bi ,  Yann Mignot ,  Nelson Felix ,  Ekmini A. De Silva

IPC: G03F1/22 ,  G03F7/20 ,  G03F7/42

Abstract: A method of removing layers of an extreme ultraviolet (EUV) pattern stack is provided. The method includes forming one or more resist templates on an upper hardmask layer. The method further includes exposing portions of the surface of the upper hardmask layer to a dry etch process to produce modified and activated surfaces. The method further includes etching the modified and activated surfaces to expose an underlying organic planarization layer.

公开(公告)号：US10431646B2

公开(公告)日：2019-10-01

申请号：US15911626

申请日：2018-03-05

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Xuefeng Liu ,  Chi-Chun Liu ,  Yongan Xu

IPC: H01L49/02 ,  H01L21/3105 ,  H01L23/522

Abstract: Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.

公开(公告)号：US20180315834A1

公开(公告)日：2018-11-01

申请号：US15948554

申请日：2018-04-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xuefeng Liu ,  Peng Xu ,  Yongan Xu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/6656 ,  H01L29/7827

Abstract: A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin.

公开(公告)号：US10090164B2

公开(公告)日：2018-10-02

申请号：US15404465

申请日：2017-01-12

Applicant: International Business Machines Corporation

Inventor： Ekmini A. De Silva ,  Isabel C. Estrada-Raygoza ,  Yann A. M. Mignot ,  Indira P. V. Seshadri ,  Yongan Xu

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/06

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block patterning. The method includes forming a first hard mask on a substrate. Spacers are formed on the first hard mask, and a second hard mask is formed over the spacers. The second hard mask and a portion of the first hard mask are concurrently removed by the same hard mask removal process to expose a surface of the substrate. After concurrently removing the second hard mask and portions of the first hard mask, the heights of the spacers are substantially equal.

公开(公告)号：US20180197745A1

公开(公告)日：2018-07-12

申请号：US15897390

申请日：2018-02-15

Applicant: International Business Machines Corporation

Inventor： Ekmini A. De Silva ,  Isabel C. Estrada-Raygoza ,  Yann A. M. Mignot ,  Indira P. V. Seshadri ,  Yongan Xu

IPC: H01L21/308 ,  H01L29/06 ,  H01L21/3105

CPC classification number: H01L21/3081 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31051 ,  H01L29/0657

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block patterning. The method includes forming a first hard mask on a substrate. Spacers are formed on the first hard mask, and a second hard mask is formed over the spacers. The second hard mask and a portion of the first hard mask are concurrently removed by the same hard mask removal process to expose a surface of the substrate. After concurrently removing the second hard mask and portions of the first hard mask, the heights of the spacers are substantially equal.