公开(公告)号：US20150236024A1

公开(公告)日：2015-08-20

申请号：US14184756

申请日：2014-02-20

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Pooja R. Batra ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Johnathan E. Faltermeier ,  Reinaldo A. Vega

IPC: H01L27/108 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L27/10867 ,  H01L21/743 ,  H01L21/7687 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/66181 ,  H01L29/785 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments for the present invention provide a semiconductor device and methods for fabrication. In an embodiment of the present invention, a semiconductor structure comprises a first conductor horizontally formed on a semiconductor substrate. A second conductor is vertically formed in a semiconductor stack that includes the semiconductor substrate. An oxidized region is formed proximate to the first conductor. The second conductor is formed in a manner to be in electrical communication with the first conductor. The first conductor is formed in a manner to be laterally connected to the second conductor. The first conductor is formed in a manner to not traverse beneath the oxidized region. The first conductor is formed in a manner to have a reduced link-up resistance with adjacent epitaxial material included in the semiconductor structure.

Abstract translation: 本发明的实施例提供一种半导体器件及其制造方法。 在本发明的实施例中，半导体结构包括水平地形成在半导体衬底上的第一导体。 第二导体垂直地形成在包括半导体衬底的半导体堆叠中。 在第一导体附近形成氧化区域。 第二导体以与第一导体电连通的方式形成。 第一导体以横向连接到第二导体的方式形成。 第一导体以不会在氧化区域下方穿过的方式形成。 第一导体以与包括在半导体结构中的相邻外延材料具有降低的连接电阻的方式形成。

公开(公告)号：US09093534B2

公开(公告)日：2015-07-28

申请号：US13953024

申请日：2013-07-29

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Bruce B. Doris ,  Ali Khakifirooz ,  Edward J. Nowak ,  Kern Rim

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/785

Abstract: An array of stacks containing a semiconductor fins and an oxygen-impermeable cap is formed on a semiconductor substrate with a substantially uniform areal density. Oxygen-impermeable spacers are formed around each stack, and the semiconductor substrate is etched to vertically extend trenches. Semiconductor sidewalls are physically exposed from underneath the oxygen-impermeable spacers. The oxygen-impermeable spacers are removed in regions in which semiconductor fins are not needed. A dielectric oxide material is deposited to fill the trenches. Oxidation is performed to convert a top portion of the semiconductor substrate and semiconductor fins not protected by oxygen-impermeable spacers into dielectric material portions. Upon removal of the oxygen-impermeable caps and remaining oxygen-impermeable spacers, an array including semiconductor fins and dielectric fins is provided. The dielectric fins alleviate variations in the local density of protruding structures, thereby reducing topographical variations in the height of gate level structures to be subsequently formed.

Abstract translation: 在半导体衬底上形成具有基本均匀的面密度的包含半导体鳍片和不透氧帽的叠层阵列。 在每个堆叠周围形成不透氧的间隔物，并且蚀刻半导体衬底以垂直延伸沟槽。 半导体侧壁从不透氧间隔物的下方物理暴露。 在不需要半导体散热片的区域中去除不透氧隔离物。 沉积电介质氧化物材料以填充沟槽。 执行氧化以将半导体衬底的顶部部分和不被不透氧隔离物保护的半导体鳍片转换成电介质材料部分。 在除去不透氧的盖子和剩余的不透氧隔离物之后，提供了包括半导体鳍片和介电鳍片的阵列。 介电散热片减轻突出结构的局部密度的变化，从而减少随后形成的栅极层结构的高度的形貌变化。

公开(公告)号：US20150200276A1

公开(公告)日：2015-07-16

申请号：US14156489

申请日：2014-01-16

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/66818

Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.

Abstract translation: 在半导体散热片上形成栅极结构之后，在形成凸起的有源区之前，使用定向离子束在半导体鳍片的端壁上形成与半导体鳍片的长度方向垂直的绝缘材料部分。 方向离子束的角度选择为包括半导体鳍片的长度方向的垂直平面，从而避免在半导体鳍片的纵向侧壁上形成电介质材料部分。 执行半导体材料的选择性外延以从半导体鳍片的侧壁表面生长凸起的有源区域。 可选地，可以在选择性外延工艺之前去除电介质材料部分的水平部分。 此外，可以在选择性外延工艺之后任选地去除电介质材料部分。

公开(公告)号：US20150004802A1

公开(公告)日：2015-01-01

申请号：US14487213

申请日：2014-09-16

Applicant: International Business Machines Corporation

Inventor： Deok-kee Kim ,  Kenneth T. Settlemyer, JR. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy J. Dalton ,  Katherina E. Babich ,  Arpan P. Mohorowala ,  Harald Okorn-Schmidt

IPC: H01L21/033

CPC classification number: H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

Abstract translation: 增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。 提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。 这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

公开(公告)号：US20130161745A1

公开(公告)日：2013-06-27

申请号：US13628225

申请日：2012-09-27

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Huiming Bu ,  Ramachandra Divakaruni ,  Bruce B. Doris ,  Chung-Hsun Lin ,  Huiling Shang ,  Tenko Yamashita

IPC: H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78621

Abstract: In one embodiment a transistor structure includes a gate stack disposed on a surface of a semiconductor body. The gate stack has a layer of gate dielectric surrounding gate metal and overlies a channel region in the semiconductor body. The transistor structure further includes a source having a source extension region and a drain having a drain extension region formed in the semiconductor body, where each extension region has a sharp, abrupt junction that overlaps an edge of the gate stack. Also included is a punch through stopper region having an implanted dopant species beneath the channel in the semiconductor body between the source and the drain. There is also a shallow channel region having an implanted dopant species located between the punch through stopper region and the channel. Both bulk semiconductor and silicon-on-insulator transistor embodiments are described.

Abstract translation: 在一个实施例中，晶体管结构包括设置在半导体本体的表面上的栅极堆叠。 栅极堆叠具有围绕栅极金属的栅极电介质层，并且覆盖半导体主体中的沟道区域。 晶体管结构还包括具有源极延伸区域和漏极的源极，该漏极延伸区域形成在半导体本体中，其中每个延伸区域具有与栅极叠层的边缘重叠的尖锐的突变结。 还包括在源极和漏极之间的半导体本体中的通道下方具有注入的掺杂物质的穿孔停止区域。 还存在具有位于穿通止动区域和通道之间的注入的掺杂剂物质的浅沟道区域。 描述了体半导体和绝缘体上硅晶体管实施例。

公开(公告)号：US20230197595A1

公开(公告)日：2023-06-22

申请号：US17555489

申请日：2021-12-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Katsuyuki Sakuma ,  Mukta Ghate Farooq ,  Ramachandra Divakaruni

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/14 ,  H01L23/538 ,  H01L23/13 ,  H01L21/48

CPC classification number: H01L23/49833 ,  H01L25/0652 ,  H01L24/16 ,  H01L24/81 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/145 ,  H01L23/5385 ,  H01L23/13 ,  H01L21/4857 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14361 ,  H01L2224/16225 ,  H01L2224/81815 ,  H01L2225/0652 ,  H01L2225/06517 ,  H01L2225/06589

Abstract: A packaged device that carries multiple component devices uses a back-mounted structure to reduce the area of the substrates in the package. The package includes a first organic laminate substrate and a second organic laminate substrate. The first organic laminate substrate is the base substrate of the packaged device. The second organic laminate substrate has higher wiring density than the first organic laminate substrate. The second organic laminate substrate is joined to a top surface (or module mounting side) of the first organic laminate substrate. A first component device is mounted on a top surface of the second organic laminate substrate. A second component device is mounted on a bottom surface of the second organic laminate substrate. The second component device recesses into a cavity at the top surface of the first organic laminate substrate.

公开(公告)号：US10541177B2

公开(公告)日：2020-01-21

申请号：US16214935

申请日：2018-12-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jeehwan Kim ,  Juntao Li ,  Devendra K. Sadana

IPC: H01L21/84 ,  H01L27/12 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L29/167 ,  H01L21/326 ,  H01L21/265 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78

Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

公开(公告)号：US10388795B2

公开(公告)日：2019-08-20

申请号：US15895541

申请日：2018-02-13

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L21/225 ,  H01L21/324

Abstract: A vertical transistor includes a gate structure interposed between a proximate spacer doped with a first dopant-type and a distal spacer doped with the first dopant-type. The proximate spacer is formed on an upper surface of a semiconductor substrate. At least one channel region extends vertically from the proximate doping source layer to the distal doping source layer. A proximate S/D extension region is adjacent the proximate spacer and a distal S/D extension region is adjacent the distal spacer. The proximate and distal S/D extension regions include dopants that match the first dopant-type of the proximate and distal doping sources.

公开(公告)号：US20190206866A1

公开(公告)日：2019-07-04

申请号：US16292934

申请日：2019-03-05

Applicant: International Business Machines Corporation

Inventor： Ramachandra Divakaruni ,  Sameer H. Jain ,  Viraj Y. Sardesai ,  Keith H. Tabakman

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/66545

Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.

公开(公告)号：US10170628B2

公开(公告)日：2019-01-01

申请号：US15840122

申请日：2017-12-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni

IPC: H01L21/84 ,  H01L29/786 ,  H01L27/12 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

Abstract: A method for forming a semiconductor device includes etching a semiconductor layer using a gate structure and spacers as a mask to protect portions of the semiconductor layer that extend beyond the gate structure. Undercuts are formed in a buried dielectric layer under the gate structure. Source and drain regions are epitaxially growing and wrapped around the semiconductor layer by forming the source and drain regions adjacent to the gate structure on a first side of the semiconductor layer and in the undercuts on a second side of the semiconductor layer opposite the first side.