-
41.发明申请公开(公告)号：US20220405125A1
公开(公告)日：2022-12-22
申请号：US17351478
申请日：2021-06-18
发明人： DEREK E. WILLIAMS , GUY L. GUTHRIE , HUGH SHEN
摘要： In at least some embodiments, a store-type operation is received and buffered within a store queue entry of a store queue associated with a cache memory of a processor core capable of executing multiple simultaneous hardware threads. A thread identifier indicating a particular hardware thread among the multiple hardware threads that issued the store-type operation is recorded. An indication of whether the store queue entry is a most recently allocated store queue entry for buffering store-type operations of the hardware thread is also maintained. While the indication indicates the store queue entry is a most recently allocated store queue entry for buffering store-type operations of the particular hardware thread, the store queue extends a duration of a store gathering window applicable to the store queue entry. For example, the duration may be extended by decreasing a rate at which the store gathering window applicable to the store queue entry ends.
-
公开(公告)号：US20210342275A1
公开(公告)日：2021-11-04
申请号：US16862785
申请日：2020-04-30
发明人： DEREK E. WILLIAMS , GUY L. GUTHRIE , HUGH SHEN , LUKE MURRAY
IPC分类号： G06F12/128
摘要： An upper level cache receives from an associated processor core a plurality of memory access requests including at least first and second memory access requests of differing first and second classes. Based on class histories associated with the first and second classes of memory access requests, the upper level cache initiates, on the system interconnect fabric, a first interconnect transaction corresponding to the first memory access request without first issuing the first memory access request to the lower level cache via a private communication channel between the upper level cache and the lower level cache. The upper level cache initiates, on the system interconnect fabric, a second interconnect transaction corresponding to the second memory access request only after first issuing the second memory access request to the lower level cache via the private communication channel between the upper level cache and the lower level cache and receiving a response to the second memory access request from the lower level cache.
-
公开(公告)号：US20200183843A1
公开(公告)日：2020-06-11
申请号：US16216624
申请日：2018-12-11
发明人： DEREK E. WILLIAMS , GUY L. GUTHRIE , HUGH SHEN
IPC分类号： G06F12/0842 , G06F12/1027
摘要： A multiprocessor data processing system includes a processor core having a translation structure for buffering a plurality of translation entries. In response to receipt of a translation invalidation request, the processor core determines from the translation invalidation request that the translation invalidation request does not require draining of memory referent instructions for which address translation has been performed by reference to a translation entry to be invalidated. Based on the determination, the processor core invalidates the translation entry in the translation structure and confirms completion of invalidation of the translation entry without regard to draining from the processor core of memory access requests for which address translation was performed by reference to the translation entry.
-
44.发明申请公开(公告)号：US20200034236A1
公开(公告)日：2020-01-30
申请号：US16049721
申请日：2018-07-30
发明人： DEREK E. WILLIAMS , GUY L. GUTHRIE , HUGH SHEN , SANJEEV GHAI , HUNG DOAN
IPC分类号： G06F11/14 , G06F12/0802 , G06F17/50 , G06F9/30
摘要： In a processing unit, a processor core executes instructions in a plurality of simultaneous hardware threads, where multiple of the plurality of hardware threads concurrently execute memory transactions. A transactional memory circuit in the processing unit tracks transaction footprints of the memory transactions of the multiple hardware thread. In response to detecting failure of a given memory transaction of one of the plurality of multiple threads due to an overflow condition, the transactional memory circuit transitions to a throttled operating mode and reduces a number of hardware threads permitted to concurrently execute memory transactions.
-
公开(公告)号：US20190220409A1
公开(公告)日：2019-07-18
申请号：US15873366
申请日：2018-01-17
发明人： GUY L. GUTHRIE , MICHAEL S. SIEGEL , WILLIAM J. STARKE , JEFFREY A. STUECHELI , DEREK E. WILLIAMS
IPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0817
摘要： A cache coherent data processing system includes at least non-overlapping first, second, and third coherency domains. A master in the first coherency domain of the cache coherent data processing system selects a scope of an initial broadcast of an interconnect operation from among a set of scopes including (1) a remote scope including both the first coherency domain and the second coherency domain, but excluding the third coherency domain that is a peer of the first coherency domain, and (2) a local scope including only the first coherency domain. The master then performs an initial broadcast of the interconnect operation within the cache coherent data processing system utilizing the selected scope, where performing the initial broadcast includes the master initiating broadcast of the interconnect operation within the first coherency domain.
-
公开(公告)号：US20180350426A1
公开(公告)日：2018-12-06
申请号：US15615313
申请日：2017-06-06
发明人： SANJEEV GHAI , GUY L. GUTHRIE , HUGH SHEN , DEREK E. WILLIAMS
IPC分类号： G11C11/406 , G06F9/54 , G06F9/30 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3012 , G06F12/084 , G06F12/0871 , G06F12/0873 , G06F12/0897 , G06F2212/601
摘要： A data processing system includes a plurality of processor cores each having a respective store-through upper level cache and a store-in banked lower level cache. Store requests of the plurality of processor cores destined for the banked lower level cache are buffered in multiple store queues including a first store queue and a second store queue. In response to determining that the multiple store queues contain store requests targeting a common bank of the banked lower level cache, store requests from the first store queue are temporarily favored for selection for issuance to the banked lower level cache over those in the second store queue.
-
公开(公告)号：US20180052609A1
公开(公告)日：2018-02-22
申请号：US15243628
申请日：2016-08-22
发明人： GUY L. GUTHRIE , DEREK E. WILLIAMS
IPC分类号： G06F3/06 , G06F12/0897 , G06F13/40
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F12/063 , G06F12/0811 , G06F12/0831 , G06F13/16 , G06F13/4068 , G06F2212/1008 , G06F2212/1016
摘要： A lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed, as well as a barrier request that requests ordering of memory access requests prior to and after the barrier request. The barrier request precedes a copy-type request and a paste-type request of the memory move in program order. Prior to completion of processing of the barrier request, the lower level cache allocates first and second state machines to service the copy-type and paste-type requests. The first state machine speculatively reads a data granule identified by a source real address of the copy-type request into a non-architected buffer. After processing of the barrier request is complete, the second state machine writes the data granule from the non-architected buffer to a storage location identified by a destination real address of the paste-type request.
-
公开(公告)号：US20170177499A1
公开(公告)日：2017-06-22
申请号：US14977841
申请日：2015-12-22
发明人： GUY L. GUTHRIE , HUGH SHEN , DEREK E. WILLIAMS
CPC分类号： G06F12/1045 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/524 , G06F12/0808 , G06F12/0815 , G06F12/084 , G06F12/0842 , G06F12/1027 , G06F2212/1024 , G06F2212/621 , G06F2212/682 , G06F2212/683
摘要： In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is removed and buffered in sidecar logic. While the translation invalidation request is buffered in the sidecar logic, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request. Subsequent memory referent instructions are ordered with respect to the broadcast synchronization request by a synchronization instruction.
-
公开(公告)号：US20170060760A1
公开(公告)日：2017-03-02
申请号：US14871682
申请日：2015-09-30
CPC分类号： G06F12/0875 , G06F3/061 , G06F3/0613 , G06F3/0656 , G06F3/067 , G06F9/30043 , G06F2212/1044 , G06F2212/452
摘要： In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation operation in response to detecting a barrier instruction in the instruction sequence immediately preceding the store instruction in program order and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.
-
公开(公告)号：US20170060757A1
公开(公告)日：2017-03-02
申请号：US14839264
申请日：2015-08-28
CPC分类号： G06F12/0875 , G06F3/061 , G06F3/0613 , G06F3/0656 , G06F3/067 , G06F9/30043 , G06F2212/1044 , G06F2212/452
摘要： In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is marked as a high priority store operation operation in response to detecting a barrier instruction in the instruction sequence immediately preceding the store instruction in program order and is not so marked otherwise. The store operation is buffered in a store queue associated with a cache memory of the processor core. Handling of the store operation in the store queue is expedited in response to the store operation being marked as a high priority store operation and not expedited otherwise.
摘要翻译： 在至少一些实施例中，处理器核心通过在指令序列中执行存储指令来产生存储操作。 响应于在程序顺序中紧接在存储指令之前的指令序列中检测到障碍指令，存储操作被标记为高优先级存储操作操作，否则没有标记。 存储操作被缓存在与处理器核心的高速缓冲存储器相关联的存储队列中。 响应于存储操作被标记为高优先级存储操作而加快存储操作在存储队列中的处理，否则不加速。
-
-
-
-
-
-
-
-
-
搜索结果
107 条记录 (耗时 0.03 秒)
