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    Compiler managed memory for image processor
    42.
    发明授权
    Compiler managed memory for image processor 有权

    公开(公告)号：US10685422B2

    公开(公告)日：2020-06-16

    申请号：US16272819

    申请日：2019-02-11

    Applicant: Google LLC

    Inventor： Albert Meixner ,  Hyunchul Park ,  Qiuling Zhu ,  Jason Rupert Redgrave

    IPC: G09G3/36 ,  G06T1/60 ,  G06F9/38 ,  G06T1/20 ,  G06F9/30

    Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.

    VIRTUAL LINEBUFFERS FOR IMAGE SIGNAL PROCESSORS
    44.
    发明申请
    VIRTUAL LINEBUFFERS FOR IMAGE SIGNAL PROCESSORS 审中-公开

    公开(公告)号：US20200120287A1

    公开(公告)日：2020-04-16

    申请号：US16659702

    申请日：2019-10-22

    Applicant: Google LLC

    Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

    IPC: H04N5/262 ,  G06T1/20 ,  G06T1/60

    Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

    Shift register with reduced wiring complexity
    45.
    发明授权
    Shift register with reduced wiring complexity 有权

    公开(公告)号：US10477164B2

    公开(公告)日：2019-11-12

    申请号：US15595403

    申请日：2017-05-15

    Applicant: Google LLC

    Inventor： Jason Rupert Redgrave

    IPC: H04N9/04 ,  G06T1/20 ,  G11C19/38 ,  H04N5/907 ,  G06F15/173 ,  G06F15/80 ,  G11C7/10 ,  H01P5/12 ,  H03K19/177 ,  G11C19/00 ,  G11C19/28

    Abstract: A shift register is described. The shift register includes a plurality of cells and register space. The shift register includes circuitry having inputs to receive shifted data and outputs to transmit shifted data, wherein: i) circuitry of cells physically located between first and second logically ordered cells are configured to not perform any logical shift; ii) circuitry of cells coupled to receive shifted data transmitted by an immediately preceding logically ordered cell comprises circuitry for writing into local register space data received at an input assigned an amount of shift specified in a shift command being executed by the shift register, and, iii) circuitry of cells coupled to transmit shifted data to an immediately following logically ordered cell comprises circuitry to transmit data from an output assigned an incremented shift amount from a shift amount of an input that the data was received on.

    Macro I/O unit for image processor
    46.
    发明授权
    Macro I/O unit for image processor 有权

    公开(公告)号：US10380969B2

    公开(公告)日：2019-08-13

    申请号：US15389168

    申请日：2016-12-22

    Applicant: Google LLC

    Inventor： Albert Meixner ,  Neeti Desai ,  Dilan Manatunga ,  Jason Rupert Redgrave ,  William Mark

    IPC: G09G5/00 ,  G06T1/20 ,  G09G5/02

    Abstract: An image processor is described. The image processor includes an I/O unit to read input image data from external memory for processing by the image processor and to write output image data from the image processor into the external memory. The I/O unit includes multiple logical channel units. Each logical channel unit is to form a logical channel between the external memory and a respective producing or consuming component within the image processor. Each logical channel unit is designed to utilize reformatting circuitry and addressing circuitry. The addressing circuitry is to control addressing schemes applied to the external memory and reformatting of image data between external memory and the respective producing or consuming component. The reformatting circuitry is to perform the reformatting.

    Shift register with reduced wiring complexity
    48.
    发明授权
    Shift register with reduced wiring complexity 有权

    公开(公告)号：US10313641B2

    公开(公告)日：2019-06-04

    申请号：US15352260

    申请日：2016-11-15

    Applicant: Google LLC

    Inventor： Jason Rupert Redgrave

    IPC: G06T1/20 ,  G11C7/10 ,  H01P5/12 ,  H04N9/04 ,  G06F15/80 ,  G11C19/00 ,  G11C19/28 ,  G11C19/38 ,  H04N5/907 ,  G06F15/173 ,  H03K19/177

    Abstract: A shift register is described. The shift register includes a plurality of cells and register space. The shift register includes circuitry having inputs to receive shifted data and outputs to transmit shifted data, wherein: i) circuitry of cells physically located between first and second logically ordered cells are configured to not perform any logical shift; ii) circuitry of cells coupled to receive shifted data transmitted by an immediately preceding logically ordered cell comprises circuitry for writing into local register space data received at an input assigned an amount of shift specified in a shift command being executed by the shift register, and, iii) circuitry of cells coupled to transmit shifted data to an immediately following logically ordered cell comprises circuitry to transmit data from an output assigned an incremented shift amount from a shift amount of an input that the data was received on.

    Multi-functional execution lane for image processor
    49.
    发明授权
    Multi-functional execution lane for image processor 有权

    公开(公告)号：US10185560B2

    公开(公告)日：2019-01-22

    申请号：US15591955

    申请日：2017-05-10

    Applicant: Google LLC

    Inventor： Artem Vasilyev ,  Jason Rupert Redgrave ,  Albert Meixner ,  Ofer Shacham

    IPC: G06F9/30 ,  G06F7/57 ,  G06F15/80

    Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.

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