Abstract:
An active grating, a three-dimensional display device and a three-dimensional display method are provided. The three-dimensional display device comprises: a display panel (1) and an active grating (2) disposed oppositely; a face recognition module, configured to acquire a distance from a current viewer to the active grating (2); a first calculating module, in signal connection with the face recognition module, configured to calculate a theoretical horizontal width of each of the light shielding regions (21) when the current viewer see an ideal 3D image at a current position, according to the distance acquired by the face recognition module and a first corresponding relationship between the distance from the current viewer to the active grating and the theoretical horizontal width of each of the light shielding region of the active grating when the current viewer see the ideal 3D image; and an adjusting module, in signal connection with the first calculating module and a driving circuit of the active grating respectively, configured to send a corresponding first control instruction to the driving circuit according to the theoretical horizontal width calculated by the first calculating module so as to adjust an actual horizontal width of each of the light shielding regions (21) of the active grating, so that the actual horizontal width equals to the theoretical horizontal width. The three-dimensional display device provided by embodiments of the invention can change the viewing region position according to position coordinates of the viewer, so that the ideal 3D image can be seen by the viewer not positioned at a fixed viewing region position, thus, improving practicality of the three-dimensional display device obviously.
Abstract:
The present disclosure provides a method and a device for modulating image display quality of a display device. The method includes: debugging a display device to a modulation state, so that a common voltage of the display device corresponding to a predetermined gray level is a standard voltage; and modulating a common voltage of the display device corresponding to other controllable gray level into a preset value, wherein there is a first preset relationship between the preset value and the standard voltage.
Abstract:
A tiled display panel and a tiled display device are disclosed. The tiled display panel includes: at least first and second adjacent display areas; a splice area disposed between the first and second adjacent display areas; a first optical element and a second optical element respectively disposed on the first and second display areas and located on two sides of the splice area; and a reflective element disposed on the splice area. Each of the first optical element and the second optical element is configured to direct at least a portion of light emitted from its respective display area to the reflective element, such that the at least a portion of light is reflected by the reflective element and then emitted out from the splice area.
Abstract:
An array substrate and a manufacturing method thereof, comprising a base substrate, and a gate, a gate insulating layer, an active layer and a source/drain arranged on the base substrate, the array substrate further comprising an antenna for receiving and/or transmitting wireless signals, the antenna being arranged on the base substrate. By arranging the antenna on the base substrate of the array substrate, the antenna is integrated directly in the display panel. Thus, not only the area of the PCB circuit board in the display device can be reduced, but also the spare area in the array substrate can be utilized sufficiently, thereby improving the integration level of the display device and reducing the total volume of the display device.
Abstract:
The disclosure provides a display panel, a method for driving the display panel and a 3D display device including the display panel, and relates to the technical field of display. The display panel comprises a display unit and at least one timing control units, wherein the display unit comprises a plurality of display regions and the plurality of display regions are simultaneously scanned. With the present invention, wire impedance in the display panel is reduced, charging time for a single row of pixels can be reduced and charging rate of the pixels can be improved.
Abstract:
The present invention discloses a gate driving method of a pixel transistor and a gate drive circuit, as well as a display device including the gate drive circuit, which falls within the field of display technology. The method comprises the steps of: a gate drive circuit outputting a preset first voltage to a gate driving line of a pixel row prior to a transistor turn-on time of the pixel row, wherein the first voltage is greater than a transistor turn-off voltage; and the gate drive circuit outputting a transistor turn-on voltage to the gate driving line of the pixel row when it reaches the transistor turn-on time. Use of the present invention can improve the accuracy of pixel display.
Abstract:
A boosting circuit, a backlight driving circuit and a backlight module are provided. The boosting circuit comprises a boosting chip (U1), an energy-storage inductor (L1), a freewheeling diode (D1), a first capacitor (C1), and a current mirror unit (U2), wherein an input terminal of an inputting branch of the current mirror unit (U2) IS connected with the cathode of the freewheeling diode (D1), and an output terminal of the inputting branch is connected with the signal input terminal (Vin) of the boosting circuit through a first resistor (R1), an input terminal of an outputting branch of the current mirror unit (U2) IS connected with the cathode of the freewheeling diode (D1), an output terminal of the outputting branch is grounded through a second resistor (R2), an ungrounded terminal of the second resistor (R2) is connected with a signal feedback pin of the boosting chip. The boosting circuit realizes the tracking of changes of the input voltage by the output voltage under the precondition that parameters of respective elements are unchanged, and achieves the effect that a voltage difference between the output voltage and the input voltage is fixed.
Abstract:
The disclosure provides a synchronous display method of an spliced display screen which comprises at least two spliced display units and at least two timing controllers respectively corresponding to the spliced display units, wherein the method comprises steps of: receiving, by each timing controller, a timing control signal for a current frame of the corresponding spliced display unit, feedback from the spliced display unit corresponding to the timing controller; determining, by each timing controller, a phase difference between the timing control signal for the current frame of the corresponding spliced display unit and a reference timing control signal received by the timing controller; judging, by each timing controller, whether or not the phase difference goes beyond a predetermined threshold range; if it is judged that the phase difference goes beyond the predetermined threshold range, generating a phase adjustment value, by the timing controller, based on the phase difference, wherein the phase adjustment value is less than the phase difference; generating, by each timing controller, a next timing control signal for a next frame of the corresponding spliced display unit, based on the phase adjustment value, so that a next phase difference between the next timing control signal for the next frame and the reference timing control signal is the phase adjustment value; and outputting the next timing control signal for the next frame to the corresponding spliced display unit. Meanwhile, the disclosure also provides a timing controller used in this synchronous display method and a spliced display screen to which this synchronous display method is applied.
Abstract:
A thin film transistor array substrate, a driving method therefore, and a liquid crystal display are disclosed. The thin film transistor array substrate includes at least a sub-pixel region formed by a gate line and a data line intersected with each other, wherein, each sub-pixel comprises a first transistor (21) of which the gate is connected with a gate line and the drain is connected with a data line and a first storage capacitor (23) of which one end is connected with the source of the first transistor (21) and the other end is connected with an output of a reference voltage, the sub-pixel further comprises a second storage capacitor (24) and a second transistor (25), wherein one end of the second storage capacitor (24) is connected with the source of the first transistor (21), and the other end of the second storage capacitor (24) is connected with the drain of the second transistor (25); the source of the second transistor (25) is connected with the output of the reference voltage, and the gate of the second transistor (25) is connected with an output of an Enable signal. Since a second storage capacitor (24) is additionally added to each sub-pixel in the thin film transistor array substrate, the capacitance of the storage capacitors during static display is increased, the voltage conversion frequency during static display is deceased, and the system power consumption is decreased.