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公开(公告)号：US09395795B2
公开(公告)日：2016-07-19
申请号：US14032335
申请日：2013-09-20
Applicant: Apple Inc.
Inventor： David S. Warren , Inna Levit , Timothy R. Paaske
CPC classification number: G06F1/3296 , G06F1/06 , G06F1/08 , G06F1/3206 , G06F1/3237 , G06F1/325 , G06F13/4022 , G06F13/4282 , Y02D10/128 , Y02D10/151 , Y02D50/20
Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.
Abstract translation: 公开了可以允许管理计算系统的功率的装置和方法的实施例。 该装置可以包括时钟发生电路，总线接口单元和控制电路。 时钟发生电路可以被配置为产生多个时钟信号。 每个时钟信号可以提供与耦合到通信总线的设备内的不同功能块的定时参考。 总线接口单元可以被配置为经由通信总线从设备接收消息。 消息可以包括延迟值和激活低功率模式的请求。 控制电路可以被配置为取决于等待时间值和多个阈值的多个时钟信号中的一个或多个。
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公开(公告)号：US20150149673A1
公开(公告)日：2015-05-28
申请号：US14089237
申请日：2013-11-25
Applicant: Apple Inc.
Inventor： Deniz Balkan , Gurjeet S. Saund , Jim J. Lin , Timothy R. Paaske , Ben D. Jarrett
IPC: G06F13/40 , G06F13/362
CPC classification number: G06F13/405 , G06F13/362 , G06F13/364 , G06F13/4027
Abstract: Embodiments of a bridge unit and system are disclosed that may allow for processing fence commands send to multiple bridge units. Each bridge unit may process a respective portion of a plurality of transactions generated by a master unit. The master unit may be configured to send a fence command to each bridge unit, which may stall the processing of the command. Each bridge unit may be configured to determine if all transactions included in its respective portion of the plurality of transactions has completed. Once each bridge unit has determined that all other bridge units have received the fence command and that all other bridge units have completed their respective portions of the plurality of transactions that were received prior to receiving the fence command, all bridge units may execute the fence command.
Abstract translation: 公开了桥单元和系统的实施例，其可以允许处理围栏命令发送到多个桥单元。 每个桥单元可以处理由主单元生成的多个交易的相应部分。 主单元可以被配置为向每个桥单元发送fence命令，这可能阻止命令的处理。 每个桥单元可以被配置为确定包括在其多个事务的相应部分中的所有事务是否已经完成。 一旦每个桥接单元已经确定所有其他桥接单元已经接收到围栏命令，并且所有其他桥接单元已经完成了在接收到围栏命令之前接收到的多个事务的各自部分，则所有桥单元可以执行fence命令 。
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公开(公告)号：US20150033061A1
公开(公告)日：2015-01-29
申请号：US13951763
申请日：2013-07-26
Applicant: Apple Inc.
Inventor： Shu-Yi Yu , Timothy R. Paaske
CPC classification number: G06F21/50 , G06F1/04 , G06F21/558 , G06F21/755
Abstract: A system for monitoring a clock input signal including a reference clock to be monitored, a flip-flop, a plurality of delay logic blocks, a sampling unit, and a comparison unit. The reference clock may have an expected maximum frequency. The flip-flop may be configured to generate a corresponding clock signal at a reduced frequency compared to the reference clock. The plurality of delay logic blocks may be configured to receive the reduced frequency clock signal and delay the signal for various amounts of time, each less than an expected period of the reference clock. The sampling unit may be configured to sample the signals output from the plurality of delay logic blocks. The comparison unit may be configured to receive the outputs of the flip-flop and the sampling unit and use these outputs to determine if the reference clock is running at an acceptable frequency compared to the expected frequency.
Abstract translation: 一种用于监视包括要监视的参考时钟，触发器，多个延迟逻辑块，采样单元和比较单元的时钟输入信号的系统。 参考时钟可能具有预期的最大频率。 触发器可以被配置为以与参考时钟相比降低的频率产生对应的时钟信号。 多个延迟逻辑块可以被配置为接收降频时钟信号并将信号延迟各种时间量，每个时间量小于参考时钟的期望周期。 采样单元可以被配置为对从多个延迟逻辑块输出的信号进行采样。 比较单元可以被配置为接收触发器和采样单元的输出，并且使用这些输出来确定参考时钟是否以与期望频率相比在可接受的频率下运行。
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公开(公告)号：US20140082242A1
公开(公告)日：2014-03-20
申请号：US13622266
申请日：2012-09-18
Applicant: APPLE INC.
Inventor： Michael W. Murphy , Joshua P. de Cesare , Timothy R. Paaske
IPC: G06F13/24
CPC classification number: G06F13/24 , G06F1/3253 , Y02D10/151
Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.
Abstract translation: 描述了一种用于减少主机和端点之间的外围组件互连快速（PCIe）链路中的延迟的方法和系统。 在所描述的实施例中，使用PCIe链路从端点向主机发出中断。 然后，当中断在主机处于等待状态时，PCIe链路被阻止进入功率节省模式，退出延迟大于预定时间段。
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公开(公告)号：US11941108B2
公开(公告)日：2024-03-26
申请号：US17652517
申请日：2022-02-25
Applicant: Apple Inc.
Inventor： Timothy R. Paaske , Weihua Mao , Shu-Yi Yu
CPC classification number: G06F21/46 , G06F21/44 , G06F21/602 , G06F21/606 , G06F21/85 , H04L9/088 , G06F2221/2137
Abstract: An apparatus, a method, and a system are presented in which the apparatus includes an interface control circuit that may be configured to receive a message including a cryptographic keyword and a policy value. The policy value may include one or more data bits indicative of one or more policies that define allowable usage of the cryptographic keyword. The apparatus also includes a security circuit that may be configured to extract the cryptographic keyword and the policy value from the message, and to apply at least one policy of the one or more policies to usage of the cryptographic keyword in response to a determination that an authentication of the message succeeded.
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Patent Agency Ranking
公开(公告)号：US11630903B1
公开(公告)日：2023-04-18
申请号：US17081276
申请日：2020-10-27
Applicant: Apple Inc.
Inventor： Timothy R. Paaske , Mitchell D. Adler , Conrad Sauerwald , Fabrice L. Gautier , Shu-Yi Yu
Abstract: In an embodiment, a system is provided in which the private key is managed in hardware and is not visible to software. The system may provide hardware support for public key generation, digital signature generation, encryption/decryption, and large random prime number generation without revealing the private key to software. The private key may thus be more secure than software-based versions. In an embodiment, the private key and the hardware that has access to the private key may be integrated onto the same semiconductor substrate as an integrated circuit (e.g. a system on a chip (SOC)). The private key may not be available outside of the integrated circuit, and thus a nefarious third party faces high hurdles in attempting to obtain the private key.
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公开(公告)号：US11481019B1
公开(公告)日：2022-10-25
申请号：US16994372
申请日：2020-08-14
Applicant: Apple Inc.
Inventor： Timothy R. Paaske , Josh P. de Cesare
IPC: G06F1/3287 , G06F1/26 , G06F9/4401 , G06F3/06 , G06F11/20
Abstract: Techniques are disclosed relating a computer system in a power-down state receiving a communication from a remote computer system and performing a task indicated by the communication. The computer system in a power-down state performs the task without transitioning from the power-down state into a power-up state. Exemplary tasks performed in the power-down state include uploading one or more files to a remote computer system, downloading one or more files from a remote computer system, deleting one or more files from the computer system, accessing input/output devices, disabling the computer system, and performing a memory check on the computer system.
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公开(公告)号：US20220179944A1
公开(公告)日：2022-06-09
申请号：US17652517
申请日：2022-02-25
Applicant: Apple Inc.
Inventor： Timothy R. Paaske , Weihua Mao , Shu-Yi Yu
Abstract: An apparatus, a method, and a system are presented in which the apparatus includes an interface control circuit that may be configured to receive a message including a cryptographic keyword and a policy value. The policy value may include one or more data bits indicative of one or more policies that define allowable usage of the cryptographic keyword. The apparatus also includes a security circuit that may be configured to extract the cryptographic keyword and the policy value from the message, and to apply at least one policy of the one or more policies to usage of the cryptographic keyword in response to a determination that an authentication of the message succeeded.
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公开(公告)号：US11181971B2
公开(公告)日：2021-11-23
申请号：US16780817
申请日：2020-02-03
Applicant: Apple Inc.
Inventor： David S. Warren , Inna Levit , Timothy R. Paaske
IPC: G06F1/3296 , G06F1/06 , G06F1/3206 , G06F13/40 , G06F13/42 , G06F1/3234 , G06F1/08 , G06F1/3237
Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.
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公开(公告)号：US10915402B2
公开(公告)日：2021-02-09
申请号：US16129726
申请日：2018-09-12
Applicant: Apple Inc.
Inventor： Zhimin Chen , Timothy R. Paaske , Yannick L. Sierra , Anish C. Trivedi
Abstract: A method for verifying program flow during execution of a software program in a computer system is disclosed. Program code of the software program includes multiple program instructions and checkpoint data structures, where a given checkpoint data structure is associated with a given program instruction and is linked to at least one other checkpoint data structure. A fault monitor circuit may receive a particular checkpoint data structure and compare the particular checkpoint data structure to a previously received checkpoint data structure that is associated with another program instruction. Based on results of the comparison, the software fault monitor circuit may signal a program flow error.
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