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公开(公告)号：US20200150745A1
公开(公告)日：2020-05-14
申请号：US16746121
申请日：2020-01-17
Applicant: Apple Inc.
Inventor： Anand Dalal , Joshua P. de Cesare
IPC: G06F1/3287 , G06F1/3293 , G06F1/3231 , G06F1/3215 , G06F1/3209 , G06F9/4401
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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公开(公告)号：US20180349609A1
公开(公告)日：2018-12-06
申请号：US15721502
申请日：2017-09-29
Applicant: Apple Inc.
Inventor： Joshua P. de Cesare , Timothy R. Paaske , Xeno S. Kovah , Nikolaj Schlej , Jeffrey R. Wilcox , Hardik K. Doshi , Kevin H. Alderfer , Corey T. Kallenberg
CPC classification number: G06F21/575 , G06F9/4401 , G06F21/73 , G06F21/79
Abstract: A method and apparatus for protecting boot variables is disclosed. A computer system includes a main processor and an auxiliary processor. The auxiliary processor includes a non-volatile memory that stores variables associated with boot code that is also stored thereon. The main processor may send a request to the auxiliary processor to alter one of the variables stored in the non-volatile memory. Responsive to receiving the request, the auxiliary processor may execute a security policy to determine if the main processor meets the criteria for altering the variable. If the auxiliary processor determines that the main processor meets the criteria, it may grant permission to alter the variable.
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3.发明申请公开(公告)号：US20170177256A1
公开(公告)日：2017-06-22
申请号：US15447328
申请日：2017-03-02
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
CPC classification number: G06F12/0223 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F3/0625 , G06F3/0632 , G06F3/0634 , G06F3/0673 , G06F9/4406 , G06F12/0646 , G06F13/1668 , G06F13/4068 , G06F13/4265 , G06F2212/1032 , G11C11/40615 , Y02D10/122 , Y02D10/151 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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公开(公告)号：US20150227476A1
公开(公告)日：2015-08-13
申请号：US14691244
申请日：2015-04-20
Applicant: Apple Inc.
Inventor： Michael W. Murphy , Joshua P. de Cesare , Timothy R. Paaske
CPC classification number: G06F13/24 , G06F1/3253 , Y02D10/151
Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.
Abstract translation: 描述了一种用于减少主机和端点之间的外围组件互连快速（PCIe）链路中的延迟的方法和系统。 在所描述的实施例中，使用PCIe链路从端点向主机发出中断。 然后，当中断在主机处于等待状态时，PCIe链路被阻止进入功率节省模式，退出延迟大于预定时间段。
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公开(公告)号：US11263326B2
公开(公告)日：2022-03-01
申请号：US15721365
申请日：2017-09-29
Applicant: Apple Inc.
Inventor： Joshua P. de Cesare , Timothy R. Paaske , Xeno S. Kovah , Nikolaj Schlej , Jeffrey R. Wilcox , Ezekiel T. Runyon , Hardik K. Doshi , Kevin H. Alderfer , Corey T. Kallenberg
IPC: G06F9/4401 , G06F21/57 , G06F21/44
Abstract: A method and apparatus for performing a secure boot of a computer system is disclosed. A computer system according to the disclosure includes an auxiliary processor and a main processor. The boot process includes initially booting the auxiliary processor. The auxiliary processor includes a non-volatile memory storing boot code for the main processor. The auxiliary processor may perform a verification of the boot code. Subsequent to verifying the boot code, the main processor may be released from a reset state. Once the main processor is no longer in the reset state, the boot code may be provided thereto. Thereafter, the boot procedure may continue with the main processor executing the boot code.
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Patent Agency Ranking
公开(公告)号：US11216054B2
公开(公告)日：2022-01-04
申请号：US16578132
申请日：2019-09-20
Applicant: Apple Inc.
Inventor： Joshua P. de Cesare , Jonathan J. Andrews , Jeffrey R. Wilcox
IPC: G06F1/32 , G06F1/3231 , G06F1/3296 , G06Q10/10 , G06F1/3203 , H04W4/02
Abstract: This application relates to techniques that adjust the sleep states of a computing device based on user proximity detection procedures. The technique includes detecting a first pattern, using a first subset of sensors of one or more sensors coupled to the computing device, to determine if the object is proximate to the computing device. Provided the first pattern is not indicative of the object being proximate to the computing device, the technique detects a second pattern, using a second subset of sensors of the one or more sensors, to determine if the object is proximate to the computing device. Furthermore, provided either the first pattern or the second pattern is indicative of the object being proximate to the computing device and provided a first portion of a computer system within the computing device is operating within a low-power sleep state, the technique causes the first portion to enter into a high-power sleep state.
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公开(公告)号：US10706825B2
公开(公告)日：2020-07-07
申请号：US14869148
申请日：2015-09-29
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Arthur L. Spence , Joshua P. de Cesare , Ilie Garbacea , Guy Cote , Mahesh B. Chappalli , Malcolm D. Gray , Christopher P. Tann
Abstract: Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals, the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value. If the timestamp is earlier than the global timer value, the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory. The display control unit may then apply the updates of the frame configuration set to its pixel processing elements. After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display.
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公开(公告)号：US20170364139A1
公开(公告)日：2017-12-21
申请号：US15691903
申请日：2017-08-31
Applicant: Apple Inc.
Inventor： Anand Dalal , Joshua P. de Cesare
CPC classification number: G06F1/3287 , G06F1/3209 , G06F1/3215 , G06F1/3231 , G06F1/3293 , G06F9/4418 , G06F9/44505 , Y02D10/122 , Y02D10/171 , Y02D10/173 , Y02D10/43 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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公开(公告)号：US09778728B2
公开(公告)日：2017-10-03
申请号：US14289775
申请日：2014-05-29
Applicant: Apple Inc.
Inventor： Anand Dalal , Joshua P. de Cesare
CPC classification number: G06F1/3287 , G06F1/3209 , G06F1/3215 , G06F1/3231 , G06F1/3293 , G06F9/4418 , G06F9/44505 , Y02D10/122 , Y02D10/171 , Y02D10/173 , Y02D10/43 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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公开(公告)号：US20170092236A1
公开(公告)日：2017-03-30
申请号：US14869148
申请日：2015-09-29
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Arthur L. Spence , Joshua P. de Cesare , Ilie Garbacea , Guy Cote , Mahesh B. Chappalli , Malcolm D. Gray
IPC: G09G5/395
CPC classification number: G09G5/395 , G06F3/1407 , G06F3/147 , G09G2310/08 , G09G2340/0407 , G09G2340/0464 , G09G2360/127
Abstract: Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals, the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value. If the timestamp is earlier than the global timer value, the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory. The display control unit may then apply the updates of the frame configuration set to its pixel processing elements. After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display.
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