公开(公告)号：US20190385669A1

公开(公告)日：2019-12-19

申请号：US16012366

申请日：2018-06-19

Applicant: Apple Inc.

Inventor： Rakesh L. Notani ,  Kai Lun Hsiung ,  Peter Fu

IPC: G11C11/406 ,  G11C8/18 ,  G11C5/14

Abstract: A memory controller includes a state machine that initiates a memory refresh of a DRAM (having a number of banks) by sending thereto a refresh command. Responsive to receiving the command, the DRAM may perform a per-bank refresh in which individual ones of the banks are refreshed in succession, one at a time. Upon receiving a high priority transaction, a determination is made as to the number of memory banks that have currently been refreshed in the per-bank refresh. If the number of banks refreshed is less than a threshold value, the per-bank refresh is aborted.

公开(公告)号：US10510396B1

公开(公告)日：2019-12-17

申请号：US16012366

申请日：2018-06-19

Applicant: Apple Inc.

Inventor： Rakesh L. Notani ,  Kai Lun Hsiung ,  Peter Fu

IPC: G11C7/00 ,  G11C11/406 ,  G11C5/14 ,  G11C8/18

Abstract: A memory controller includes a state machine that initiates a memory refresh of a DRAM (having a number of banks) by sending thereto a refresh command. Responsive to receiving the command, the DRAM may perform a per-bank refresh in which individual ones of the banks are refreshed in succession, one at a time. Upon receiving a high priority transaction, a determination is made as to the number of memory banks that have currently been refreshed in the per-bank refresh. If the number of banks refreshed is less than a threshold value, the per-bank refresh is aborted.

公开(公告)号：US10408863B2

公开(公告)日：2019-09-10

申请号：US15848804

申请日：2017-12-20

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Fabien S. Faure ,  Rakesh L. Notani

IPC: G11C7/10 ,  G01R19/165 ,  G11C5/14 ,  G11C8/12 ,  G11C5/02

Abstract: A method and apparatus for predicting a reference voltage in a memory subsystem is disclosed. A memory subsystem includes a memory controller coupled to a memory. The memory controller includes a lookup table having a number of different reference voltage values each corresponding to one of a number of different performance states. The memory controller further includes calibration circuitry configured to determine reference voltages for operation in various performance states. Responsive to returning to a performance state after operating in another, the calibration circuitry may restore the reference voltage to its most recently used value, and also obtain a predicted reference voltage. Calibrations may be performed at both the restored reference voltage and the predicted reference voltage obtained from the lookup table. The subsequent operating reference voltage may then be selected based on which of the two calibrations resulted in the largest data eye width.

公开(公告)号：US20190196740A1

公开(公告)日：2019-06-27

申请号：US15849945

申请日：2017-12-21

Applicant: Apple Inc.

Inventor： Rakesh L. Notani ,  Robert E. Jeter

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0683

Abstract: A method and apparatus for performing performance state changes are disclosed. A power management circuit may be configured to receive requests for changes to first and second performance states for at least at least one memory of a plurality of memories. In response to a determination that a change to the first performance state is in progress, when the request to change to the second performance state is received, the power management controller may send a notification to a controller coupled to the memories. The controller may halt scheduling of memory interface calibration operations for the at least one memory based on the notification.

公开(公告)号：US10175905B2

公开(公告)日：2019-01-08

申请号：US15263833

申请日：2016-09-13

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Liang Deng ,  Kai Lun Hsiung ,  Manu Gulati ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Venkata Ramana Malladi ,  Gregory S. Mathews ,  Enming Zheng ,  Fabien S. Faure

IPC: G06F1/32 ,  G06F3/06 ,  G06F1/08 ,  G06F13/16 ,  G06F13/42

Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

公开(公告)号：US10083736B1

公开(公告)日：2018-09-25

申请号：US15190291

申请日：2016-06-23

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Fabien S. Faure

IPC: G11C7/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4091

CPC classification number: G11C11/4076 ,  G06F13/16 ,  G06F13/1689 ,  G11C7/1066 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A method and apparatus for adaptive calibration scheduling is disclosed. A calibration circuit may perform calibrations of a delay applied to a data strobe conveyed from a memory controller to the memory, and may also calibrate a reference voltage. After calibrating the data strobe delay, a current width of an eye opening and a current score are determined. If the eye opening is not less than a minimum threshold and the current score is within a specified range of a reference score, the reference voltage calibration, if conditionally scheduled, is inhibited. The results of the calibration may be recorded in a history table. A timer may advance a pointer provided to a sequence table at a rate determined by information stored in the history table. Information stored in an entry of the sequence table may indicate which calibration procedures are to be performed during the next calibration cycle.

公开(公告)号：US09928890B2

公开(公告)日：2018-03-27

申请号：US15249962

申请日：2016-08-29

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Alma L. Juarez Dominguez

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/222 ,  G11C11/401 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015

Abstract: A system and method for calibrating memory using credit-based segmentation control is disclosed. A memory and a memory controller coupled thereto. The memory controller includes a calibration circuit configured to calibrate a data strobe signal conveyed to/from the memory. The calibration may be subdivided, in time, into a number of segments. The memory controller also includes a credit circuit configured to provide a condition code to the calibration circuit. The condition code may be indicative of an amount of time a request has been pending, or how many request are pending. If the condition code indicates that a request has been pending for more than a certain amount of time, the calibration may be terminated.

公开(公告)号：US09286961B1

公开(公告)日：2016-03-15

申请号：US14672412

申请日：2015-03-30

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kiran B. Kattel

IPC: G11C7/22 ,  G11C8/18 ,  H03L7/08

CPC classification number: H03L7/08 ,  G11C7/1093 ,  G11C7/22

Abstract: A method and apparatus for reducing a number of delay elements used in providing a delayed data strobe signal is disclosed. The method includes determining a number of delay elements of a master delay locked loop (DLL) needed to provide a calibrated delay of a clock signal (i.e. the data strobe). The method also include determining an integer number of half clock periods within the calibrated delay, and determining a second number of delay elements within the calibrated delay. If the integer number of half clock periods within the calibrated delay is zero, a slave DLL may be programmed with the first number of delay elements. However, if the number of half clock periods is non-zero, then a third number of delay elements is calculated by subtracting the second number of delay elements from the first number. Thereafter, the slave DLL is programmed with the third number of delay elements.

Abstract translation: 公开了一种用于减少用于提供延迟的数据选通信号的延迟元件的数量的方法和装置。 该方法包括确定提供时钟信号（即，数据选通）的校准延迟所需的主延迟锁定环（DLL）的延迟元件的数量。 该方法还包括确定校准延迟内的半个时钟周期的整数，以及确定校准延迟内的第二数量的延迟元件。 如果校准延迟内的半个时钟周期的整数为零，则可以用第一数量的延迟元件对从属DLL进行编程。 然而，如果半个时钟周期的数量是非零，则通过从第一个数字减去第二个延迟元素数来计算第三个延迟元件数。 此后，从动DLL用第三数量的延迟元件编程。