公开(公告)号：US07391595B2

公开(公告)日：2008-06-24

申请号：US11155739

申请日：2005-06-20

申请人： Chun-Ying Chen

发明人： Chun-Ying Chen

IPC分类号： H02H9/00

CPC分类号： G05F1/571

摘要： During start-up of a circuit having a high voltage supply and a low voltage supply, a backup bias generator (BBG) is used to avoid burnout and exceeding a breakdown voltage. The high voltage supply is powered on before the low voltage supply. The BBG generates bias in response to the high voltage supply being powered on. Once the low voltage supply is powered on and is stable, the BBG is shut down so that it does not interfere with normal operation of the circuit. The circuit can be separated into high and low supply domains without breakdown issues during power start-up, allowing for power and area optimization.

摘要翻译： 在启动具有高电压电源和低电压电源的电路时，使用备用偏置发生器（BBG）来避免烧坏并超过击穿电压。 高压电源在低电压供电之前通电。 BBG响应高电压供电而产生偏置。 一旦低压电源通电并且稳定，则BBG被关闭，使其不干扰电路的正常工作。 该电路可以分为高电源和低电源域，而在启动启动期间不会出现故障，从而实现功率和面积优化。

公开(公告)号：US20070152761A1

公开(公告)日：2007-07-05

申请号：US11636977

申请日：2006-12-12

申请人： Kwang Kim ,  Chun-Ying Chen ,  Mark Chambers

发明人： Kwang Kim ,  Chun-Ying Chen ,  Mark Chambers

IPC分类号： H03L7/00

CPC分类号： H03L7/0995 ,  H03L7/093 ,  H03L7/18 ,  H03L2207/06

摘要： An embodiment of the invention provides an apparatus and method for varying a voltage controlled oscillator (VCO) sensitivity. A VCO has an oscillator portion coupled to a variable current supply. The variable current supply has one or more enabled variable current cells. The enable variable current cell input provides a control to change the VCO sensitivity. In an example, the oscillator portion has a ring oscillator. In an example, the variable current supply has at least two variable current cells that supply the control current. A binary control signal alters a quantity of variable current cells that supply the control current. Each successive variable current cell has an output current substantially equal to twice that of a prior variable current cell.

摘要翻译： 本发明的实施例提供了一种用于改变压控振荡器（VCO）灵敏度的装置和方法。 VCO具有耦合到可变电流源的振荡器部分。 可变电流源具有一个或多个使能的可变电流单元。 使能可变电流单元输入提供了改变VCO灵敏度的控制。 在一个示例中，振荡器部分具有环形振荡器。 在一个示例中，可变电流源具有提供控制电流的至少两个可变电流单元。 二进制控制信号改变提供控制电流的可变电流单元的数量。 每个连续的可变电流单元具有基本上等于先前可变电流单元的输出电流的两倍的输出电流。

公开(公告)号：US20070132628A1

公开(公告)日：2007-06-14

申请号：US11637823

申请日：2006-12-13

申请人： Chun-Ying Chen

发明人： Chun-Ying Chen

IPC分类号： H03M1/12

CPC分类号： H03M1/002

摘要： In an embodiment, an analog to digital converter (ADC) has a dynamic power circuit. The ADC has a track-and-hold circuit with an output and a track mode. The ADC also has a comparator with an input. A preamplifier is coupled between the track-and-hold output and the comparator input. At least one of a preamplifier current and a comparator current are limited during the track mode to reduce ADC power consumption.

摘要翻译： 在一个实施例中，模数转换器（ADC）具有动态功率电路。 ADC具有跟踪和保持电路，具有输出和跟踪模式。 ADC还具有一个带有输入的比较器。 前置放大器耦合在跟踪保持输出和比较器输入之间。 在跟踪模式期间，前置放​​大器电流和比较器电流中的至少一个受到限制，以降低ADC功耗。

公开(公告)号：US07161443B2

公开(公告)日：2007-01-09

申请号：US10952932

申请日：2004-09-30

申请人： Chun-Ying Chen

发明人： Chun-Ying Chen

IPC分类号： H03B5/32

CPC分类号： H03L1/027 ,  H03L7/081 ,  H03L7/183

摘要： An environmental-compensated oscillator includes a reference clock waveform generator; a phase locked loop receiving the reference clock waveform and outputting a phase locked clock waveform; and a sensor outputting a voltage corresponding to an environmental parameter of the generator. The voltage is used by the PLL to compensate the phase locked clock waveform. The PLL includes a phase detector, a charge pump coupled to an output of the phase detector, a low pass filter coupled to an output of the charge pump, a voltage controlled oscillator (“VCO”) coupled to an output of the low pass filter, and a feedback path coupled between an output of the VCO and the phase detector, wherein the feedback path includes a phase rotator capable of fine tuning an output frequency of the VCO responsive to a frequency of an input clock. An accumulator is coupled to the phase rotator and supplies the input clock to the phase rotator. The phase rotator finely tunes the VCO output frequency. An analog-to-digital converter converts the voltage to a digital representation. The digital representation is mapped to a frequency adjustment for use by the PLL for the compensation. The environmental parameter is any of temperature, stress and power supply voltage.

摘要翻译： 环境补偿振荡器包括参考时钟波形发生器; 接收参考时钟波形并输出锁相时钟波形的锁相环; 以及输出与发电机的环境参数对应的电压的传感器。 PLL使用电压来补偿锁相时钟波形。 PLL包括相位检测器，耦合到相位检测器的输出的电荷泵，耦合到电荷泵的输出的低通滤波器，耦合到低通滤波器的输出的压控振荡器（“VCO” 以及耦合在VCO的输出和相位检测器之间的反馈路径，其中反馈路径包括能够响应于输入时钟的频率来微调VCO的输出频率的相位旋转器。 累加器耦合到相位旋转器并将输入时钟提供给相位旋转器。 相位旋转器精细调谐VCO输出频率。 模数转换器将电压转换为数字表示。 数字表示被映射到频率调整以供PLL用于补偿。 环境参数为温度，应力和电源电压中的任何一种。

公开(公告)号：US20060161370A1

公开(公告)日：2006-07-20

申请号：US11256156

申请日：2005-10-24

申请人： Xicheng Jiang ,  Chun-Ying Chen ,  Kevin Miller ,  Joel Danzig ,  Beth Wilcher

发明人： Xicheng Jiang ,  Chun-Ying Chen ,  Kevin Miller ,  Joel Danzig ,  Beth Wilcher

IPC分类号： G01R35/00

CPC分类号： H03K5/135 ,  H03M9/00 ,  H04J3/0685 ,  H04L7/0037 ,  H04L7/0331 ,  H04L7/04 ,  H04L25/14

摘要： Systems and methods for pulse stretching architectures for phase alignment of multi-frequency clocks for high speed data acquisitions are disclosed. A high speed data acquisition system includes a transmitter and a receiver. The receiver includes a multi-frequency clock generator that generates a plurality of clock signals, a pattern check module that detects a test pattern received from the transmitter and outputs a stretch command signal, and a stretch pulse generator that receives the stretch command signal and provides a stretch pulse signal that aligns the phases of the plurality of clock signals generated by the multi-frequency clock generator. Methods for initializing and shifting multi-phase clock signals to optimize error performance of a high speed data acquisition system are also provided.

摘要翻译： 公开了用于用于高速数据采集的多频时钟的相位对准的脉冲拉伸架构的系统和方法。 高速数据采集系统包括发射机和接收机。 接收机包括：多频时钟发生器，产生多个时钟信号;模式检查模块，用于检测从发送器接收的测试模式并输出拉伸命令信号;以及拉伸脉冲发生器，其接收拉伸命令信号并提供 拉伸脉冲信号，其对准由多频时钟发生器产生的多个时钟信号的相位。 还提供了用于初始化和移位多相时钟信号以优化高速数据采集系统的误差性能的方法。

公开(公告)号：US20060071728A1

公开(公告)日：2006-04-06

申请号：US10952932

申请日：2004-09-30

申请人： Chun-Ying Chen

发明人： Chun-Ying Chen

IPC分类号： H03B5/32

CPC分类号： H03L1/027 ,  H03L7/081 ,  H03L7/183

摘要： An environmental-compensated oscillator includes a reference clock waveform generator; a phase locked loop receiving the reference clock waveform and outputting a phase locked clock waveform; and a sensor outputting a voltage corresponding to an environmental parameter of the generator. The voltage is used by the PLL to compensate the phase locked clock waveform. The PLL includes a phase detector, a charge pump coupled to an output of the phase detector, a low pass filter coupled to an output of the charge pump, a voltage controlled oscillator (“VCO”) coupled to an output of the low pass filter, and a feedback path coupled between an output of the VCO and the phase detector, wherein the feedback path includes a phase rotator capable of fine tuning an output frequency of the VCO responsive to a frequency of an input clock. An accumulator is coupled to the phase rotator and supplies the input clock to the phase rotator. The phase rotator finely tunes the VCO output frequency. An analog-to-digital converter converts the voltage to a digital representation. The digital representation is mapped to a frequency adjustment for use by the PLL for the compensation. The environmental parameter is any of temperature, stress and power supply voltage.

摘要翻译： 环境补偿振荡器包括参考时钟波形发生器; 接收参考时钟波形并输出锁相时钟波形的锁相环; 以及输出与发电机的环境参数对应的电压的传感器。 PLL使用电压来补偿锁相时钟波形。 PLL包括相位检测器，耦合到相位检测器的输出的电荷泵，耦合到电荷泵的输出的低通滤波器，耦合到低通滤波器的输出的压控振荡器（“VCO” 以及耦合在VCO的输出和相位检测器之间的反馈路径，其中反馈路径包括能够响应于输入时钟的频率来微调VCO的输出频率的相位旋转器。 累加器耦合到相位旋转器并将输入时钟提供给相位旋转器。 相位旋转器精细调谐VCO输出频率。 模数转换器将电压转换为数字表示。 数字表示被映射到频率调整以供PLL用于补偿。 环境参数为温度，应力和电源电压中的任何一种。

公开(公告)号：US20050174166A1

公开(公告)日：2005-08-11

申请号：US11104496

申请日：2005-04-13

申请人： Ralph Duncan ,  Chun-Ying Chen ,  Young Shin

发明人： Ralph Duncan ,  Chun-Ying Chen ,  Young Shin

IPC分类号： H04H20/00 ,  H03D3/00 ,  H03D7/14 ,  H03H11/04 ,  H03B1/00

CPC分类号： H03H11/04 ,  H03D3/008 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1483 ,  H03D7/165 ,  H03D2200/0025 ,  H03D2200/0043 ,  H03D2200/0047 ,  H04B1/30

摘要： An integrated circuit formed on a semiconductor chip, comprising a low pass filter circuit having a first resistor of a first resistance value and a capacitor of a first capacitance value, wherein the first resistance value and the first capacitance value determine a corner frequency of the filter; and a tuning circuit having a second resistor of a second resistance value, a switched-capacitor of a third resistance value and a comparator that compares two voltage signals to produce a control signal, wherein the control signal adjusts the first and second resistance values as a function of the third resistance value. The corner frequency of the filter can be adjusted by varying one or more reference voltage signals. In combination, the corner frequency of the filter is adjusted by changing the frequency of a clock that controls the switched-capacitor to decrease the circuit sensitivity.

公开(公告)号：US20050088142A1

公开(公告)日：2005-04-28

申请号：US10694188

申请日：2003-10-28

申请人： Chun-Ying Chen

发明人： Chun-Ying Chen

IPC分类号： H02J7/00

CPC分类号： H02J7/0073

摘要： A method and system, compatible with low-voltage CMOS technology, for controlling the charging of a battery. The method includes monitoring a battery voltage with respect to a threshold voltage. The method further includes coupling a charging control logic supply to ground, generating an active low first control signal, inverting the active low first control signal, and charging the battery at a first rate when the battery voltage is below the threshold voltage. The method further includes coupling the charging control logic supply to the battery voltage, generating an active high second control signal, and charging the battery at a second rate when the battery voltage exceeds the threshold voltage. The first charging rate is slower than the second charging rate. The method further includes supplying battery power to a charger line when the battery voltage exceeds the charger voltage, and suppressing a leakage current.

摘要翻译： 一种兼容低压CMOS技术的方法和系统，用于控制电池的充电。 该方法包括监测相对于阈值电压的电池电压。 该方法还包括将充电控制逻辑电源耦合到接地，产生有效低电平第一控制信号，使有效低电平第一控制信号反相，以及当电池电压低于阈值电压时，以第一速率向电池充电。 该方法还包括：当电池电压超过阈值电压时，将充电控制逻辑电源耦合到电池电压，产生有效高的第二控制信号，并以第二速率对电池充电。 第一充电速率比第二充电速率慢。 该方法还包括当电池电压超过充电器电压并且抑制泄漏电流时，向充电器线路提供电池电力。

公开(公告)号：US08536614B2

公开(公告)日：2013-09-17

申请号：US13339388

申请日：2011-12-29

申请人： Chih-Hao Hsu ,  Rong Xuan ,  Yu-Hsiang Chang ,  Jung-Chun Huang ,  Chun-Ying Chen

发明人： Chih-Hao Hsu ,  Rong Xuan ,  Yu-Hsiang Chang ,  Jung-Chun Huang ,  Chun-Ying Chen

IPC分类号： H01L33/00

CPC分类号： H01L33/38 ,  H01L33/14 ,  H01L33/22 ,  H01L33/40

摘要： A nitride semiconductor light emitting device including an n-type nitride semiconductor layer, a p-type nitride semiconductor layer, a light emitting semiconductor layer, a first metal pad, a second metal pad, and a first magnetic material layer is provided. The light emitting semiconductor layer is disposed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer. The first metal pad is electrically connected to the n-type nitride semiconductor layer. The second metal pad is electrically connected to the p-type nitride semiconductor layer. The first magnetic material layer is disposed between the first metal pad and the n-type nitride semiconductor layer. A distribution area of the first magnetic material layer parallel to a (0001) plane of the n-type nitride semiconductor layer is greater than or equal to an area of the first metal pad parallel to the (0001) plane.

摘要翻译： 提供了包括n型氮化物半导体层，p型氮化物半导体层，发光半导体层，第一金属焊盘，第二金属焊盘和第一磁性材料层的氮化物半导体发光器件。 发光半导体层设置在n型氮化物半导体层和p型氮化物半导体层之间。 第一金属焊盘电连接到n型氮化物半导体层。 第二金属焊盘电连接到p型氮化物半导体层。 第一磁性材料层设置在第一金属焊盘和n型氮化物半导体层之间。 与n型氮化物半导体层的（0001）面平行的第一磁性体层的分布面积大于或等于平行于（0001）面的第一金属焊盘的面积。

公开(公告)号：US20120062311A1

公开(公告)日：2012-03-15

申请号：US13065720

申请日：2011-03-28

申请人： Chun-Ying Chen ,  Jiangfeng Wu

发明人： Chun-Ying Chen ,  Jiangfeng Wu

IPC分类号： G05F3/02

CPC分类号： H03K19/018521 ,  H03K19/018571

摘要： According to one disclosed embodiment, an adaptive voltage rail circuit for integrating low voltage devices with high voltage analog circuits is described. This adaptive voltage rail circuit includes a high voltage analog circuit having a common mode voltage. Further included is a first voltage rail having a first rail voltage which is based on and greater than the common mode voltage of the high voltage analog circuit. A second voltage rail having a second rail voltage which is based on and less than the same common mode voltage is also present. By connecting these first and second voltage rails across at least one low voltage device, an adaptive voltage rail circuit is able to safely integrate low voltage devices with high voltage analog circuits in the same system.

摘要翻译： 根据一个公开的实施例，描述了一种用于将低压器件与高压模拟电路集成的自适应电压轨电路。 该自适应电压轨电路包括具有共模电压的高压模拟电路。 还包括第一电压轨，其具有基于并且大于高压模拟电路的共模电压的第一轨电压。 还存在具有基于且小于相同共模电压的第二导轨电压的第二电压轨。 通过将这些第一和第二电压轨连接到至少一个低电压器件上，自适应电压轨电路能够将低电压器件与同一系统中的高电压模拟电路安全地集成。