公开(公告)号：US20250070785A1

公开(公告)日：2025-02-27

申请号：US18236038

申请日：2023-08-21

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Ajay Kumar DIMRI

IPC: H03L7/08 ,  G01R31/28 ,  H03K3/037 ,  H03K19/20

Abstract: A test-circuit includes a PLL-divider outputting first and third clock-signals as PLL clock-signals during functional mode and a capture-phase of transition and stuck-at-modes, and outputting a second clock-signal based upon an external clock-signal as an ATE clock-signal during a shift-phase of the transition and stuck-at-mode. An OCC passes the clock-signals in functional mode, transition capture mode, and stuck-at capture mode through sub-paths within first paths within first and second clock selection circuits so the first and third clock-signals are passed through less than the entire first paths, the sub-paths being first and second functional clock paths. In shift phase of transition and stuck-at-modes, the OCC passes the second clock-signal through sub-paths within second paths within the first and second clock selection circuits during the shift-phase so the second clock-signal is passed through less than the entire second paths, and through the first and second functional clock paths during the shift-phase.

公开(公告)号：US20250069652A1

公开(公告)日：2025-02-27

申请号：US18942973

申请日：2024-11-11

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI

IPC: G11C11/417 ,  G11C11/412

Abstract: Disclosed herein is a method of operating a static random access memory (SRAM) device in retention mode. The method includes powering an array of SRAM cells between first and second voltages in retention mode, detecting process variation information about the array of SRAM cells, and generating a control word based thereupon. The method continues with generating a reference voltage that is proportional to absolute temperature and having a magnitude curve that is set by the control word, and then maintaining the second voltage as being equal to the reference voltage.

公开(公告)号：US12237007B2

公开(公告)日：2025-02-25

申请号：US17852567

申请日：2022-06-29

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan Dhori ,  Harsh Rawat ,  Promod Kumar ,  Nitin Chawla ,  Manuj Ayodhyawasi

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

公开(公告)号：US20250061301A1

公开(公告)日：2025-02-20

申请号：US18800891

申请日：2024-08-12

Applicant: STMicroelectronics International N.V.

Inventor： Lucile MARGARIA ,  Philippe ALARY ,  Julien MERCIER

IPC: G06K19/07

Abstract: A debug method implemented by a first near field communication (NFC) device includes a step of storing, in a memory of the first NFC device, one or more parameters which are associated with the operation of the first NFC device during a communication with a second distant NFC device. The first NFC device then uses an answer to select (ATS) communication, sent in response to receipt of an answer to select (ATS) communication, to send the stored one or more parameters to the second distant NFC device.

公开(公告)号：US20250053478A1

公开(公告)日：2025-02-13

申请号：US18798040

申请日：2024-08-08

Applicant: STMicroelectronics International N.V.

Inventor： Raphael CLAUSS

IPC: G06F11/10

Abstract: A memory system includes a memory with memory blocks. A first logic circuit performs an XOR combinational logic function of a current value of a data addressing mode and of at least one bit of a first data packet including an error correction code of a data element to be written. A second data packet, generated by the first logic circuit, is stored into one of the memory blocks. A second logic circuit performs an XOR combinational logic function of at least one bit of the second packet (such as read from one of the memory blocks) and of the current value of the addressing mode. A weight of the bit of the first data packet corresponds to a weight of the at least one bit of the second read data packet.

公开(公告)号：US20250052788A1

公开(公告)日：2025-02-13

申请号：US18788967

申请日：2024-07-30

Applicant: STMicroelectronics International N.V.

Inventor： Deepak Kumar ARORA ,  Tanisha GUPTA ,  Shubham JAIN ,  Anuj GROVER

IPC: G01R13/02 ,  G11C27/02

Abstract: Systems, apparatuses, and methods for an on chip dynamic IR oscilloscope are provided. An oscilloscope circuitry may comprise sensor circuitry, voltage generator circuitry, finite state machine, and latch circuitry. The sensor circuitry may include digital logic circuitry, sample and hold circuitry, and sense amplifier circuitry. The voltage generator circuitry may include a voltage generator, analog buffers, switches, and high speed buffer. The finite state machine may control the sensor circuitry to sample a voltage waveform and the voltage generator circuitry to generate a reference voltage that may change over time. The sensing amplifier circuitry may compare the samples to the reference voltage to generate flags when a sample exceeds a reference voltage. The flags may be used to stored the voltages associated with the flags, which may be used to redraw the waveform sampled.

公开(公告)号：US20250046371A1

公开(公告)日：2025-02-06

申请号：US18790867

申请日：2024-07-31

Applicant: STMicroelectronics International N.V.

Inventor： Marco PASOTTI ,  Riccardo VIGNALI ,  Alessandro CABRINI ,  Riccardo ZURLA

IPC: G11C13/00

Abstract: An in-memory computation device receives an input signal and provides an output signal. The device includes a memory array with memory cells coupled to word lines that receive word line activation signals indicative of the input signal and coupled to bit lines that generate bit line currents; and a digital detector for sampling the bit line current and, in response, providing the output signal. A digital detector includes: a control stage that compares the bit line current with at least one reference current and generates corresponding control signals; a selection stage that generates a total selection current based on the first bit line current and on the control signals; an integration stage that samples the total selection current; and a charge counter stage that generates the output signal on the basis of a sampled first total selection current and the control signals.

公开(公告)号：US20250040163A1

公开(公告)日：2025-01-30

申请号：US18776146

申请日：2024-07-17

Applicant: STMicroelectronics International N.V.

Inventor： Riccardo DEPETRO

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/778

Abstract: For manufacturing a semiconductor electronic device a wafer is provided which has a substrate layer of semiconductor material having a first portion and a second portion distinct from the first portion. An epitaxial region of a single semiconductor material is grown on the first portion of the substrate layer. An epitaxial multilayer having a heterostructure is grown on the second portion of the substrate layer. A first electronic component based on the single semiconductor material is formed from the epitaxial region and a second electronic component based on heterostructure is formed from the heterostructure. Forming a first electronic component comprises forming a plurality of doped regions in the epitaxial region, after the step of growing an epitaxial multilayer.

公开(公告)号：US20250038391A1

公开(公告)日：2025-01-30

申请号：US18785654

申请日：2024-07-26

Applicant: STMicroelectronics International N.V.

Inventor： Vincent KNOPIK

IPC: H01P5/18

Abstract: Provided is a coupler including a first assembly of an input unit element, an intermediate unit element, and an output unit element. Each unit element includes a first coil and a second coil arranged in a cross having a general “H” shape. A first input terminal and a second input terminal of the intermediate unit element are coupled to a first output terminal and to a second output terminal of the input unit element, a first output terminal and a second output terminal of the intermediate unit element are coupled to a first input terminal and to a second input terminal of the output unit element, and the input unit element is spatially positioned between the intermediate unit element and the output unit element.

公开(公告)号：US20250035703A1

公开(公告)日：2025-01-30

申请号：US18770967

申请日：2024-07-12

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Ankur BAL ,  Aradhana KUMARI

IPC: G01R31/3185

Abstract: An integrated circuit is provided. For example, an integrated circuit comprises a functional data path and a scan-data path. At least a portion of the scan-data path is separate from the functional data path. The portion of the scan-data path which is separate from the functional data path comprises a combined gating/delay element for preventing a scan-data signal from reaching any elements downstream of the combined gating/delay element during a scan mode and for providing some or all of a desired signal delay in the portion of the scan-data path which is separate from the functional data path.