公开(公告)号：US07948040B2

公开(公告)日：2011-05-24

申请号：US12031893

申请日：2008-02-15

Applicant: Shunpei Yamazaki ,  Kengo Akimoto

Inventor： Shunpei Yamazaki ,  Kengo Akimoto

IPC: H01L29/78 ,  H01L29/786

CPC classification number: H01L29/78621 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/66757 ,  H01L2029/7863

Abstract: A semiconductor device includes a semiconductor layer overlapping with a gate electrode and having an impurity region outside a region which overlaps with the gate electrode; a first conductive layer which is provided on a side provided with the gate electrode of the semiconductor layer and partially in contact with the impurity region; an insulating layer provided over the gate electrode and the first conductive layer; and a second conductive layer which is formed in the insulating layer and in contact with the first conductive layer through an opening at least part of which overlaps with the first conductive layer.

Abstract translation: 半导体器件包括与栅电极重叠并且在与栅电极重叠的区域之外具有杂质区域的半导体层; 第一导电层，其设置在设置有半导体层的栅电极并且部分地与杂质区接触的一侧; 设置在所述栅电极和所述第一导电层上的绝缘层; 以及第二导电层，其形成在所述绝缘层中并且通过其至少一部分与所述第一导电层重叠的开口与所述第一导电层接触。

公开(公告)号：US20110084269A1

公开(公告)日：2011-04-14

申请号：US12899265

申请日：2010-10-06

Applicant: Shunpei Yamazaki ,  Suzunosuke Hiraishi ,  Kengo Akimoto ,  Junichiro Sakata

Inventor： Shunpei Yamazaki ,  Suzunosuke Hiraishi ,  Kengo Akimoto ,  Junichiro Sakata

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/45

Abstract: An object is to reduce contact resistance between an oxide semiconductor layer and source and drain electrode layers electrically connected to the oxide semiconductor layer in a thin film transistor including the oxide semiconductor layer. The source and drain electrode layers have a stacked structure of two or more layers. In this stack of layers, a layer in contact with the oxide semiconductor layer is a thin indium layer or a thin indium-alloy layer. Note that the oxide semiconductor layer contains indium. A second layer or second and any of subsequent layers in the source and drain electrode layers are formed using an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy containing any of these elements as a component, an alloy containing any of these elements in combination, or the like.

Abstract translation: 本发明的目的是减少在包括氧化物半导体层的薄膜晶体管中氧化物半导体层与与氧化物半导体层电连接的源极和漏极电极层之间的接触电阻。 源极和漏极电极层具有两层或更多层的堆叠结构。 在该堆叠层中，与氧化物半导体层接触的层是薄的铟层或薄的铟 - 合金层。 注意，氧化物半导体层含有铟。 使用选自Al，Cr，Cu，Ta，Ti，Mo和W的元素来形成源极和漏极电极层中的第二层或第二层以及后续层中的任何一层，包含任何这些元素作为组分的合金， 合并这些元素中的任何一种的合金等。

公开(公告)号：US07923356B2

公开(公告)日：2011-04-12

申请号：US11295470

申请日：2005-12-07

Applicant: Toru Takayama ,  Kengo Akimoto

Inventor： Toru Takayama ,  Kengo Akimoto

IPC: H01L21/00

CPC classification number: H01L29/66757 ,  H01L29/78666 ,  H01L29/78675

Abstract: Concerning an art related to a manufacturing method for a semiconductor device having an integrated circuit using thin film transistors on a substrate, a problem is to provide a condition for forming an amorphous silicon film having distortion. In the deposition of an amorphous silicon film using a sputter method, a condition is provided with a frequency of 15 to 25 kHz and a deposition power of 0.5 to 3 kW. This can sufficiently contain Ar at 10×1020/cm3 or more in an amorphous silicon film, thus making possible to form an amorphous silicon film having distortion.

Abstract translation: 关于具有在基板上使用薄膜晶体管的集成电路的半导体器件的制造方法的技术，存在的问题是提供一种形成具有变形的非晶硅膜的条件。 在使用溅射法沉积非晶硅膜的情况下，提供15至25kHz的频率和0.5至3kw的沉积功率的条件。 这可以在非晶硅膜中充分地含有10×10 20 / cm 3以上的Ar，因此能够形成具有变形的非晶硅膜。

公开(公告)号：US07910490B2

公开(公告)日：2011-03-22

申请号：US12432403

申请日：2009-04-29

Applicant: Kengo Akimoto ,  Tatsuya Honda ,  Norihito Sone

Inventor： Kengo Akimoto ,  Tatsuya Honda ,  Norihito Sone

IPC: H01L21/461 ,  H01L21/302

CPC classification number: H01L29/78696 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/428 ,  H01L21/465 ,  H01L21/477 ,  H01L27/1225 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7869

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

公开(公告)号：US20110062436A1

公开(公告)日：2011-03-17

申请号：US12880343

申请日：2010-09-13

Applicant: Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Ryosuke WATANABE ,  Junichiro SAKATA ,  Kengo AKIMOTO ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Hideyuki KISHIDA

Inventor： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Ryosuke WATANABE ,  Junichiro SAKATA ,  Kengo AKIMOTO ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Hideyuki KISHIDA

IPC: H01L29/12

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/04 ,  H01L29/045 ,  H01L29/78618 ,  H01L29/78693 ,  H01L29/78696

Abstract: To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.

Abstract translation: 提供具有良好的电特性和高可靠性的晶体管以及包括该晶体管的显示装置。 晶体管是使用用于沟道区的氧化物半导体形成的底栅晶体管。 使用通过热处理进行脱水或脱氢的氧化物半导体层作为活性层。 有源层包括微结晶的浅表部分的第一区域和其余部分的第二区域。 通过使用具有这种结构的氧化物半导体层，可以抑制归因于表层部分的水分进入或从表面部分的氧的消除导致的n型变化，以及寄生通道的产生。 此外，可以减小氧化物半导体层与源极和漏极之间的接触电阻。

公开(公告)号：US20110049510A1

公开(公告)日：2011-03-03

申请号：US12861190

申请日：2010-08-23

Applicant: Shunpei YAMAZAKI ,  Junichiro SAKATA ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Miyuki HOSOBA ,  Masayuki SAKAKURA ,  Yoshiaki OIKAWA

Inventor： Shunpei YAMAZAKI ,  Junichiro SAKATA ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Miyuki HOSOBA ,  Masayuki SAKAKURA ,  Yoshiaki OIKAWA

IPC: H01L33/08 ,  H01L33/16 ,  H01L21/336

CPC classification number: H01L21/477 ,  G02F1/133345 ,  G02F1/1368 ,  H01L21/02565 ,  H01L21/02664 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1251 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.

Abstract translation: 本发明的目的是提供具有优异显示特性的显示装置，其中使用具有对应于各个电路的特性的不同结构的晶体管形成设置在一个基板上的像素电路和驱动电路。 驱动器电路部分包括驱动电路晶体管，其中使用金属膜形成栅电极层，源电极层和漏电极层，并且使用氧化物半导体形成沟道层。 像素部分包括其中使用氧化物导体形成栅电极层，源电极层和漏电极层的像素晶体管，并且使用氧化物半导体形成半导体层。 像素晶体管使用透光材料形成，因此可以制造具有较高开口率的显示装置。

公开(公告)号：US20100279474A1

公开(公告)日：2010-11-04

申请号：US12768205

申请日：2010-04-27

Applicant: Kengo AKIMOTO ,  Daisuke KAWAE

Inventor： Kengo AKIMOTO ,  Daisuke KAWAE

IPC: H01L21/336

CPC classification number: H01L27/1225 ,  H01L27/1214 ,  H01L29/7869

Abstract: A formation of a gate electrode provided over an oxide semiconductor layer of a thin film transistor is performed together with a patterning of the oxide semiconductor layer.

Abstract translation: 在薄膜晶体管的氧化物半导体层上设置的栅电极的形成与氧化物半导体层的图案化一起进行。

公开(公告)号：US20100252826A1

公开(公告)日：2010-10-07

申请号：US12570498

申请日：2009-09-30

Applicant: Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Atsushi UMEZAKI

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Atsushi UMEZAKI

IPC: H01L29/786 ,  H01L21/44

CPC classification number: H01L27/124 ,  G09G3/3233 ,  G09G2310/0286 ,  G09G2310/0297 ,  H01L21/02565 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/12 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518

Abstract: With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. The increase in the numbers of gate lines and signal lines makes it difficult to mount an IC chip having a driver circuit for driving the gate line and the signal line by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit driving the pixel portion are provided over the same substrate. The pixel portion and at least a part of the driver circuit are formed using thin film transistors in each of which an oxide semiconductor is used. Both the pixel portion and the driver circuit are provided over the same substrate, whereby manufacturing costs are reduced.

Abstract translation: 随着显示装置的定义的增加，像素的数量增加，因此栅极线和信号线的数量增加。 栅极线和信号线的数量的增加使得难以安装具有用于通过接合等驱动栅极线和信号线的驱动电路的IC芯片，这导致制造成本的增加。 驱动像素部的像素部和驱动电路设置在同一基板上。 像素部分和驱动电路的至少一部分使用薄膜晶体管形成，其中每个使用氧化物半导体。 像素部分和驱动电路均设置在相同的基板上，由此降低了制造成本。

公开(公告)号：US20100117075A1

公开(公告)日：2010-05-13

申请号：US12612700

申请日：2009-11-05

Applicant: Kengo AKIMOTO ,  Shunpei YAMAZAKI

Inventor： Kengo AKIMOTO ,  Shunpei YAMAZAKI

IPC: H01L29/26

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: An object is to prevent an impurity such as moisture and oxygen from being mixed into an oxide semiconductor and suppress variation in semiconductor characteristics of a semiconductor device in which an oxide semiconductor is used. Another object is to provide a semiconductor device with high reliability. A gate insulating film provided over a substrate having an insulating surface, a source and a drain electrode which are provided over the gate insulating film, a first oxide semiconductor layer provided over the source electrode and the drain electrode, and a source and a drain region which are provided between the source electrode and the drain electrode and the first oxide semiconductor layer are provided. A barrier film is provided in contact with the first oxide semiconductor layer.

Abstract translation: 本发明的目的是防止诸如水分和氧气的杂质混入氧化物半导体中并抑制其中使用氧化物半导体的半导体器件的半导体特性的变化。 另一个目的是提供一种具有高可靠性的半导体器件。 提供在具有绝缘表面的衬底上的栅极绝缘膜，设置在栅极绝缘膜上的源极和漏极，设置在源电极和漏极上的第一氧化物半导体层，以及源极和漏极区 设置在源电极和漏电极之间以及第一氧化物半导体层。 提供与第一氧化物半导体层接触的阻挡膜。

公开(公告)号：US20100084652A1

公开(公告)日：2010-04-08

申请号：US12571549

申请日：2009-10-01

Applicant: Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC: H01L33/00

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/127 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/24 ,  H01L29/7869

Abstract: A display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area is necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and whose end portions are over the first oxide semiconductor layer and overlap with the gate electrode. The gate electrode of the non-linear element is connected to a scan line or a signal line, the first wiring layer or the second wiring layer of the non-linear element is directly connected to the gate electrode layer so as to apply potential of the gate electrode.

Abstract translation: 需要包括具有适当结构和占用面积小的氧化物半导体，保护电路等的显示装置。 保护电路使用非线性元件形成，该非线性元件包括覆盖栅电极的栅极绝缘膜; 在所述栅极绝缘层上方并与所述栅电极重叠的第一氧化物半导体层; 以及通过层叠导电层和第二氧化物半导体层而形成的第一布线层和第二布线层，并且其端部在第一氧化物半导体层上方并与栅电极重叠。 非线性元件的栅电极连接到扫描线或信号线，非线性元件的第一布线层或第二布线层直接连接到栅极电极层，以施加电位 栅电极。