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    Link adaptation method in mobile communication system and device therefor
    44.
    发明授权
    Link adaptation method in mobile communication system and device therefor 有权

    公开(公告)号：US12238723B2

    公开(公告)日：2025-02-25

    申请号：US17435217

    申请日：2020-05-06

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Sung Cheol Chang

    IPC: H04W72/21 ,  H04L1/1607 ,  H04L1/1812 ,  H04W72/1268 ,  H04W72/23

    Abstract: A method for operating a transmission node performing link adaptation in a mobile communication network may include the steps of: receiving, from a resource allocation node, resource allocation information for a resource for transmission of data; determining link adaptation information and transmitting the determined link adaptation information to a reception node; and on the basis of the determined link adaptation information, transmitting the data to the reception node. Therefore, link adaptation accurately reflecting a radio channel state between a base station and terminals can be performed, thereby enabling efficient use of a radio resource.

    CMOS logic element including oxide semiconductor
    46.
    发明授权
    CMOS logic element including oxide semiconductor 有权

    公开(公告)号：US12237331B2

    公开(公告)日：2025-02-25

    申请号：US17520853

    申请日：2021-11-08

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung Haeng Cho ,  Byung-Do Yang ,  Sooji Nam ,  Jaehyun Moon ,  Jae-Eun Pi ,  Jae-Min Kim

    IPC: H01L27/02 ,  H01L27/092 ,  H01L29/24 ,  H03K19/018 ,  H03K19/0185 ,  H03K19/0948

    Abstract: Provided is a Complementary Metal Oxide Semiconductor (CMOS) logic element. The CMOS logic element includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes an NMOS area vertically spaced apart from the PMOS area, a first transistor disposed on the PMOS area, and a second transistor disposed on the NMOS area and complementarily connected to the first transistor, wherein the first transistor includes a first gate electrode, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, wherein the second transistor includes a second gate electrode and a second channel vertically overlapping the second gate electrode, wherein the first channel includes silicon, wherein the second channel includes an oxide semiconductor.

    Radar device operating in dual mode and operation method thereof
    47.
    发明授权
    Radar device operating in dual mode and operation method thereof 有权

    公开(公告)号：US12235346B2

    公开(公告)日：2025-02-25

    申请号：US17573177

    申请日：2022-01-11

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Min Park ,  Bon Tae Koo ,  Kyung Hwan Park ,  Pil Jae Park ,  Jang Hong Choi

    IPC: G01S13/536 ,  G01S7/35 ,  G01S13/58

    Abstract: Disclosed is a radar device capable of operating in a dual mode, which includes a transmitter that includes a first signal generator that generates a Doppler radar signal and a second signal generator that generates a Frequency Modulated Continuous Wave (FMCW) radar signal, a receiver that receives a reflected signal reflected from a target and converts the reflected signal to a digital signal, a signal processing circuit that processes the digital signal differently depending on the dual mode to output an output signal, a signal analysis circuit that analyzes the output signal, and a controller that controls operations of the transmitter, the receiver, the signal processing circuit, and the signal analysis circuit, and the dual mode includes a first mode in which the first signal generator is activated and a second mode in which the second signal generator is activated.

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