知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

2471 条记录 (耗时 0.032 秒)

    System for managing memory
    41.
    发明授权
    System for managing memory 失效
    用于管理内存的系统

    公开(公告)号：US08255667B2

    公开(公告)日：2012-08-28

    申请号：US13096347

    申请日：2011-04-28

    申请人： Uri Elzur

    发明人： Uri Elzur

    IPC分类号： G06F13/00

    CPC分类号： G06F12/10 ,  G06F12/145

    摘要： Systems and methods that manage memory are provided. In one embodiment, a system for communications may include, for example, a memory management system that may handle a first application employing a virtual address based tagged offset and a second application employing a zero based tagged offset with a common set of memory algorithms.

    摘要翻译： 提供了管理内存的系统和方法。 在一个实施例中，用于通信的系统可以包括例如可以处理使用基于虚拟地址的标记偏移的第一应用的存储器管理系统，以及采用具有公共存储器算法集合的基于零的标记偏移的第二应用。

    Substitute uniform resource locator (URL) generation
    42.
    发明授权
    Substitute uniform resource locator (URL) generation 有权
    替代统一的资源定位器（URL）生成

    公开(公告)号：US08255480B2

    公开(公告)日：2012-08-28

    申请号：US11290074

    申请日：2005-11-30

    申请人： James Carlton Bedingfield, Sr. ,  John Martin Gehl

    发明人： James Carlton Bedingfield, Sr. ,  John Martin Gehl

    IPC分类号： G06F15/16

    CPC分类号： G06F17/30887 ,  H04L29/12594 ,  H04L29/12943 ,  H04L61/301 ,  H04L61/6072

    摘要： Methods of generating a substitute URL are disclosed. In one implementation, a form is presented by a web server on a web site home page for the submission of a first URL for which a user wishes to generate an alias URL. A second URL is then generated for the URL that is entered in the form. The second URL contains some indication of the web site that hosts the first URL. In a second implementation the substitute URL generation is offered through a link or button on a web page other than the web site home page. The substitute URL is generated for the URL for the web page that hosts the link. In a third implementation, a web site automatically generates substitute URLs.

    摘要翻译： 公开了生成替代URL的方法。 在一个实现中，Web站点主页上的Web服务器呈现表单，用于提交用户希望生成别名URL的第一URL。 然后，为在表单中输入的URL生成第二个URL。 第二个URL包含托管第一个URL的网站的一些指示。 在第二个实现中，替代URL生成是通过除了网站主页之外的网页上的链接或按钮提供的。 为承载链接的网页的URL生成替代URL。 在第三个实现中，网站自动生成替代URL。

    Audio encoding method with function of accelerating a quantization iterative loop process
    43.
    发明授权
    Audio encoding method with function of accelerating a quantization iterative loop process 有权
    具有加速量化迭代循环处理功能的音频编码方法

    公开(公告)号：US08255232B2

    公开(公告)日：2012-08-28

    申请号：US12183031

    申请日：2008-07-30

    申请人： Wen-Haw Wang

    发明人： Wen-Haw Wang

    IPC分类号： G10L19/00 ,  G10L19/02 ,  G10L21/00 ,  G10L19/04

    CPC分类号： G10L19/035

    摘要： An audio encoding method previously estimates better initial iterative values of global-gain and scalefactor for avoiding heavy calculation. The estimating process of the encoding method includes calculating the bit allocation of one frequency sample based on a sampling rate, a bit rate, and the number of audio channels according to an input frame, and the psychoacoustic model, searching one frequency sample having the greatest sample energy in each of a plurality of scalefactor bands, quantizing the frequency sample to comply with the bit allocation and to generate a corresponding scalefactor, searching a maximum scalefactor of all scalefactor bands corresponding to the input frame, and setting initial values of scalefactors and an initial value of global-gain for the quantization iterative loop process according to the corresponding scalefactor and the maximum scalefactor.

    摘要翻译： 音频编码方法先前估计全局增益和比例因子的更好的初始迭代值，以避免重的计算。 编码方法的估计处理包括：根据输入帧，根据输入帧，根据采样率，比特率，音频信道数，计算一个频率样本的比特分配;以及心理声学模型，搜索具有最大值的一个频率样本 在多个比例因子频带中的每一个中采样能量，量化频率样本以符合比特分配并产生相应的比例因子，搜索对应于输入帧的所有比例因子频带的最大比例因子，以及设置比例因子的初始值，以及 根据相应的比例因子和最大比例因子，量化迭代循环过程的全局增益初始值。

    Method and system for block noise reduction
    44.
    发明授权
    Method and system for block noise reduction 失效
    减少噪音的方法和系统

    公开(公告)号：US08254462B2

    公开(公告)日：2012-08-28

    申请号：US11090642

    申请日：2005-03-25

    申请人： Brian Schoner

    发明人： Brian Schoner

    IPC分类号： H04B1/66 ,  H04N7/12

    CPC分类号： H04N5/142 ,  H04N19/117 ,  H04N19/14 ,  H04N19/16 ,  H04N19/162 ,  H04N19/176 ,  H04N19/186 ,  H04N19/42 ,  H04N19/86

    摘要： In a video system, a method and system for block noise reduction are provided. Edge parameters based on spatial variance may be determined to detect vertical edges that may result from block noise. These edge parameters may be determined serially. Once detected, pixels neighboring the vertical edges may be filtered and clamped to determine a vertical block noise reduction difference (BNR) parameter. Similarly, edge parameters based on spatial variance may be determined to detect horizontal edges that may result from block noise. These edge parameters may be determined serially. Once detected, pixels neighboring the horizontal edge may be filtered and clamped to determine a horizontal BNR difference parameter. The vertical and horizontal BNR difference parameters may be utilized to reduce block noise artifacts in the video image.

    摘要翻译： 在视频系统中，提供了用于块降噪的方法和系统。 可以确定基于空间方差的边缘参数以检测可能由块噪声产生的垂直边缘。 这些边缘参数可以串联确定。 一旦被检测到，与垂直边缘相邻的像素可被滤波和钳位，以确定垂直块噪声降低差（BNR）参数。 类似地，可以确定基于空间方差的边缘参数以检测可能由块噪声产生的水平边缘。 这些边缘参数可以串联确定。 一旦被检测到，与水平边缘相邻的像素可以被滤波和钳位以确定水平BNR差参数。 可以利用垂直和水平BNR差分参数来减少视频图像中的块噪声伪影。

    Phase lock loop with phase interpolation by reference clock and method for the same
    45.
    发明授权
    Phase lock loop with phase interpolation by reference clock and method for the same 有权
    通过参考时钟进行相位插值的锁相环和相同的方法

    公开(公告)号：US08253454B2

    公开(公告)日：2012-08-28

    申请号：US12263456

    申请日：2008-11-01

    申请人： Chia-Liang Lin

    发明人： Chia-Liang Lin

    IPC分类号： H03L7/06

    CPC分类号： H03L7/07 ,  H03L7/0812 ,  H03L7/0998 ,  H03L2207/06

    摘要： The present invention relates to a PLL that utilizes a phase interpolation by a reference clock. The PLL includes a phase-interpolated controller for generating a phase-interpolation control signal; a phase/frequency detector for detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference; a loop filter for filtering the phase error signal to generate a first control signal; a phase-interpolated oscillator for generating an output clock under a control by the phase-interpolation control signal and the first control signal; and a divide-by-N circuit for dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer.

    摘要翻译： 本发明涉及利用基准时钟进行相位插值的PLL。 PLL包括用于产生相位插值控制信号的相位插值控制器; 相位/频率检测器，用于检测第二参考时钟和反馈时钟之间的相位差，并输出相位误差信号以表示相位差; 环路滤波器，用于对相位误差信号进行滤波以产生第一控制信号; 相位插值振荡器，用于在相位插值控制信号和第一控制信号的控制下产生输出时钟; 和N分频电路，用于将输出时钟除以因子N以产生反馈时钟，其中N是整数。

    Method and system for an integrated host PCI I/O bridge and dual port gigabit Ethernet controller
    46.
    发明授权
    Method and system for an integrated host PCI I/O bridge and dual port gigabit Ethernet controller 失效
    集成主机PCI I / O桥和双端口千兆以太网控制器的方法和系统

    公开(公告)号：US08249097B2

    公开(公告)日：2012-08-21

    申请号：US10887067

    申请日：2004-07-08

    申请人： Sagar W. Kenkare

    发明人： Sagar W. Kenkare

    IPC分类号： H04J3/02

    CPC分类号： H04L12/66

    摘要： Aspects of the invention may include two gigabit Ethernet controllers integrated within a single chip and an I/O bridge coupled to the two gigabit Ethernet controllers and integrated within the single chip. The system may further include an I/O function coupled to the I/O bridge that is integrated within the single chip. The I/O function may include I/O logic and an I/O buffer integrated within the single chip and coupled to the I/O bridge and/or the two gigabit Ethernet controllers. A timing function or timing block may also be coupled to the I/O bridge and integrated within the single chip. A host system may be coupled to the I/O bridge. The I/O bridge may further include a primary bus controller, which may be a primary PCI bus controller. The controller or controller block may include control and status registers that may be coupled to the primary bus controller.

    摘要翻译： 本发明的方面可以包括集成在单个芯片内的两个千兆以太网控制器以及耦合到两个千兆以太网控制器并且集成在单个芯片内的I / O桥。 该系统还可以包括耦合到集成在单个芯片内的I / O桥的I / O功能。 I / O功能可以包括集成在单个芯片内的I / O逻辑和I / O缓冲器，并且耦合到I / O桥和/或两个千兆以太网控制器。 定时功能或定时块也可以耦合到I / O桥并且集成在单个芯片内。 主机系统可以耦合到I / O桥。 I / O桥可以进一步包括主总线控制器，其可以是主PCI总线控制器。 控制器或控制器块可以包括可以耦合到主总线控制器的控制和状态寄存器。

    Crimping pliers
    47.
    发明授权
    Crimping pliers 有权
    压线钳

    公开(公告)号：US08245560B2

    公开(公告)日：2012-08-21

    申请号：US12350375

    申请日：2009-01-08

    申请人： Kurt Battenfeld ,  Thomas Glockseisen

    发明人： Kurt Battenfeld ,  Thomas Glockseisen

    IPC分类号： B21D37/14

    CPC分类号： B25B7/12 ,  B25B7/16 ,  B25B27/10 ,  B25B27/146 ,  H01R43/042

    摘要： The present invention relates to crimping pliers designed and arranged for manually crimping a work piece. Such crimping pliers comprise two manually operated hand levers coupled by a transfer mechanism with two crimping jaws. A closing mechanism is designed and arranged for being operated independent on said hand levers. Upon activation of the closing mechanism the crimping jaws are moved from an open state in a partial movement in a further closed starting state. The crimping jaws are secured in the starting state against returning into said open state. Starting from said starting state the crimping jaws are movable in an additional partial movement towards each other upon manipulation of the hand levers.

    摘要翻译： 本发明涉及设计和布置用于手工压接工件的压接钳。 这种压接钳包括两个手动操作的手柄，其通过具有两个压接爪的转移机构联接。 闭合机构被设计和布置成独立于所述手柄操作。 在关闭机构启动时，在另一闭合启动状态下，部分运动中，压接爪从打开状态移动。 压接爪在起始状态下固定，防止返回到所述打开状态。 从所述起始状态开始，在操纵手柄时，压接爪可以以额外的部分运动方式彼此移动。