公开(公告)号：US20180176468A1

公开(公告)日：2018-06-21

申请号：US15845862

申请日：2017-12-18

Applicant: QUALCOMM Incorporated

Inventor： Ye-Kui Wang ,  Geert Van der Auwera

IPC: H04N5/232 ,  G09G5/14 ,  H04N7/01

Abstract: A method of processing video data includes receiving 360-degree video data, receiving one or more first syntax elements indicating preferred regions-of-interest or preferred viewports of the 360-degree video data, receiving one or more second syntax elements that indicate a preferred rendering operation for rendering the preferred regions-of-interest or preferred viewports, and rendering the 360-degree video data based on the preferred rendering operations.

公开(公告)号：US10003815B2

公开(公告)日：2018-06-19

申请号：US14293829

申请日：2014-06-02

Applicant: QUALCOMM Incorporated

Inventor： Adarsh Krishnan Ramasubramonian ,  Ye-Kui Wang ,  Ying Chen ,  Krishnakanth Rapaka

IPC: H04N7/12 ,  H04N19/46 ,  H04N19/597 ,  H04N19/70 ,  H04N19/30 ,  H04N19/573 ,  H04N19/58

Abstract: A device may determine, based on a value, whether all cross-layer random access skipped (CL-RAS) pictures of an intra random access point (IRAP) access unit are present in a video data bitstream. In addition, the device may reconstruct pictures of the video data based at least in part on syntax elements decoded from the video data bitstream.

公开(公告)号：US09998735B2

公开(公告)日：2018-06-12

申请号：US14228031

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Jianle Chen ,  Xiang Li ,  Krishnakanth Rapaka ,  Ye-Kui Wang ,  Marta Karczewicz

IPC: H04N19/11 ,  H04N19/103 ,  H04N19/105 ,  H04N19/503 ,  H04N19/176 ,  H04N19/30 ,  H04N19/593 ,  H04N19/33 ,  H04N19/70 ,  H04N19/46

CPC classification number: H04N19/105 ,  H04N19/176 ,  H04N19/30 ,  H04N19/33 ,  H04N19/46 ,  H04N19/503 ,  H04N19/593 ,  H04N19/70

Abstract: In one implementation, an apparatus is provided for encoding or decoding video information. The apparatus comprises a memory unit configured to store reference layer pictures associated with a reference layer, an enhancement layer, or both. The apparatus further comprises a processor operationally coupled to the memory unit. In one embodiment, the processor is configured to restrict usage of at most one reference layer pictures that has a different spatial resolution than a current picture as an inter-layer reference picture, and predict the current picture using inter-layer prediction and the inter-layer reference picture.

公开(公告)号：US09992493B2

公开(公告)日：2018-06-05

申请号：US14227910

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Jianle Chen ,  Xiang Li ,  Krishnakanth Rapaka ,  Ye-Kui Wang ,  Marta Karczewicz

IPC: H04N19/103 ,  H04N19/11 ,  H04N19/109 ,  H04N19/105 ,  H04N19/503 ,  H04N19/176 ,  H04N19/30 ,  H04N19/593 ,  H04N19/33 ,  H04N19/70 ,  H04N19/46

CPC classification number: H04N19/105 ,  H04N19/176 ,  H04N19/30 ,  H04N19/33 ,  H04N19/46 ,  H04N19/503 ,  H04N19/593 ,  H04N19/70

Abstract: In one implementation, an apparatus is provided for encoding or decoding video information. The apparatus comprises a memory unit configured to store reference layer pictures associated with a reference layer, an enhancement layer, or both. The apparatus further comprises a processor operationally coupled to the memory unit. In one embodiment, the processor is configured to restrict usage of at most one reference layer pictures that has been resampled as an inter-layer reference picture, and predict a current picture using inter-layer prediction and the inter-layer reference picture.

公开(公告)号：US09930378B2

公开(公告)日：2018-03-27

申请号：US15040418

申请日：2016-02-10

Applicant: QUALCOMM Incorporated

Inventor： Fnu Hendry ,  Ying Chen ,  Ye-Kui Wang

IPC: H04N7/12 ,  H04N21/2343

CPC classification number: H04N21/234327 ,  H04N21/235 ,  H04N21/435

Abstract: A first descriptor describes an operation point. The second descriptor is a hierarchy descriptor or a hierarchy extension descriptor. The second descriptor has a hierarchy layer index value equal to a value of the second syntax element. A first value of a first syntax element in the first descriptor specifies that an elementary stream indicated by a second syntax element in the first descriptor, when not present in an elementary stream list, shall be added into the list, and an elementary stream indicated by an index in the second descriptor, when not present in the list, shall be added to the list. Responsive to determining the first syntax element has a second value different from the first value, adding the elementary stream indicated by the second syntax element, when not present in the list, into the list, but not the elementary stream indicated by the index in the second descriptor.

公开(公告)号：US09918105B2

公开(公告)日：2018-03-13

申请号：US14876699

申请日：2015-10-06

Applicant: QUALCOMM Incorporated

Inventor： Chao Pang ,  Ye-Kui Wang ,  Krishnakanth Rapaka ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N7/12 ,  H04N19/593 ,  H04N19/513 ,  H04N19/70 ,  H04N19/44 ,  H04N19/186 ,  H04N19/176 ,  H04N19/52

CPC classification number: H04N19/593 ,  H04N19/176 ,  H04N19/186 ,  H04N19/44 ,  H04N19/513 ,  H04N19/52 ,  H04N19/70

Abstract: In general, the disclosure describes techniques related to block vector coding for Intra Block Copy and Inter modes. In one example, the disclosure is directed to a video coding device comprising a memory configured to store video data and one or more processors. The video coding device is configured to determine a reference picture used for coding the current video block and determine a picture order count (POC) value for the reference picture. In response to the POC value for the reference picture being equal to a POC value for a current picture that includes the current video block, the video coding device sets a value of a syntax element to indicate that a reference picture list includes the current picture. Otherwise, the video coding device sets the value of the syntax element to indicate that the reference picture list does not include the current picture.

公开(公告)号：US09900605B2

公开(公告)日：2018-02-20

申请号：US14513034

申请日：2014-10-13

Applicant: QUALCOMM Incorporated

Inventor： Adarsh Krishnan Ramasubramonian ,  Ying Chen ,  Ye-Kui Wang ,  Fnu Hendry

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N19/187 ,  H04N19/30 ,  H04N19/46 ,  H04N19/70 ,  H04N19/80 ,  H04N19/68 ,  H04N19/86

CPC classification number: H04N19/187 ,  H04N19/30 ,  H04N19/46 ,  H04N19/68 ,  H04N19/70 ,  H04N19/80 ,  H04N19/86

Abstract: An apparatus configured to code video information includes a memory unit and a processor in communication with the memory unit. The memory unit is configured to store video information associated with a video layer having a picture. The processor is configured to determine whether the picture is a non-picture-order-count (POC)-anchor picture, and based on the determination of whether the picture is a non-POC-anchor picture, perform one of (1) refraining from indicating a POC reset in connection with the picture, or (2) indicating the POC reset in connection with the picture. The processor may encode or decode the video information.

公开(公告)号：US20170347166A1

公开(公告)日：2017-11-30

申请号：US15602988

申请日：2017-05-23

Applicant: QUALCOMM Incorporated

Inventor： Ye-Kui Wang

IPC: H04N21/845 ,  H04N19/85 ,  H04L29/06 ,  H04N21/432

CPC classification number: H04N21/8451 ,  H04L65/601 ,  H04N19/30 ,  H04N19/70 ,  H04N19/85 ,  H04N21/23439 ,  H04N21/432 ,  H04N21/8456 ,  H04N21/85406

Abstract: In one example, a device for retrieving video data includes one or more processors configured to receive data describing a sample entry type for a sample of a video bitstream, the sample entry type being one of ‘hev1’ or ‘hev2,’ wherein the sample comprises video data encoded according to one of High-Efficiency Video Coding (HEVC) or layered HEVC (L-HEVC), and wherein one or more other samples including video data precede the sample in the video bitstream in decoding order, and in response to the sample entry type being ‘hev1’ or ‘hev2’ and the sample comprising the video data encoded according to one of HEVC or L-HEVC, retrieve the sample to perform random access using the sample, without retrieving the video data of any of the one or more other samples that precede the sample, and without retrieving parameter sets of any previous samples of the video bitstream in decoding order.

公开(公告)号：US09794579B2

公开(公告)日：2017-10-17

申请号：US14330836

申请日：2014-07-14

Applicant: QUALCOMM Incorporated

Inventor： Adarsh Krishnan Ramasubramonian ,  Ying Chen ,  Ye-Kui Wang

IPC: H04N19/29 ,  H04N19/30 ,  H04N19/597 ,  H04N19/70 ,  H04N19/423

CPC classification number: H04N19/29 ,  H04N19/30 ,  H04N19/423 ,  H04N19/597 ,  H04N19/70

Abstract: A method of decoding video data comprising partitioning a decoded picture buffer (DPB) into a plurality of sub-DPBs, receiving at least one indication of a sub-DPB size for the plurality of sub-DPBs for one or more operation points of a multi-layer video coding process, and allocating memory space for the plurality of sub-DPBs based on the at least one indication.

公开(公告)号：US09762904B2

公开(公告)日：2017-09-12

申请号：US13709555

申请日：2012-12-10

Applicant: Qualcomm Incorporated

Inventor： Jianle Chen ,  Muhammed Zeyd Coban ,  Ye-Kui Wang ,  Xianglin Wang ,  Marta Karczewicz ,  Wei-Jung Chien

IPC: H04N19/51 ,  H04N19/196 ,  H04N19/52 ,  H04N19/70 ,  H04N19/463

CPC classification number: H04N19/463 ,  H04N19/196 ,  H04N19/197 ,  H04N19/52 ,  H04N19/70

Abstract: In general, techniques are described for performing motion vector prediction for video coding. A video coding device comprising a processor may perform the techniques. The processor may be configured to determine a plurality of candidate motion vectors for a current block of the video data so as to perform the motion vector prediction process and scale one or more of the plurality of candidate motion vectors determined for the current block of the video data to generate one or more scaled candidate motion vectors. The processor may then be configured to modify the scaled candidate motion vectors to be within a specified range.