公开(公告)号：US06946876B2

公开(公告)日：2005-09-20

申请号：US10705858

申请日：2003-11-13

Applicant: Takeshi Isezaki ,  Toshiro Takahashi

Inventor： Takeshi Isezaki ,  Toshiro Takahashi

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/10 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/175

CPC classification number: H03K19/00361

Abstract: Noise of a low frequency band, generated inside a logic circuit, is remarkably reduced. A semiconductor integrated circuit device is provided with: a high voltage supply circuit generating, from a high voltage external power supply that is externally input, a high voltage internal power supply having a certain voltage level; and a low voltage supply circuit generating, from a low voltage external power supply that is externally input, a low voltage internal power supply having a certain voltage level. In inputting/outputting a signal between a logic circuit block and an I/O unit, a signal level is shifted through a level shifter unit. Since the logic circuit block is operated by the high voltage internal power supply and the low voltage internal power supply, the inductance in the semiconductor integrated circuit device is not subjected directly to DC fluctuation in consumed currents. Therefore, the characteristic impedance of power supply becomes equivalently smaller, thereby reducing low frequency noise.

Abstract translation: 在逻辑电路内产生的低频带的噪声显着降低。 半导体集成电路器件具有：从外部输入的高压外部电源产生具有一定电压电平的高压内部电源的高压电源电路; 以及从外部输入的低压外部电源产生具有一定电压电平的低压内部电源的低电压电源电路。 在逻辑电路块和I / O单元之间输入/输出信号时，信号电平通过电平移位器单元移位。 由于逻辑电路块由高压内部电源和低电压内部电源操作，因此半导体集成电路器件中的电感不会直接受到消耗电流中的直流波动的影响。 因此，电源的特性阻抗变得相当小，从而降低了低频噪声。

公开(公告)号：US6154045A

公开(公告)日：2000-11-28

申请号：US218723

申请日：1998-12-22

Applicant: Yibin Ye ,  Shih-Lien Lu ,  Vivek K. De ,  Siva Narendra

Inventor： Yibin Ye ,  Shih-Lien Lu ,  Vivek K. De ,  Siva Narendra

IPC: H03K5/04 ,  H03K5/13 ,  H03K19/017 ,  H03K19/01 ,  H03K5/12 ,  H03K19/175

CPC classification number: H03K5/04 ,  H03K19/01707 ,  H03K5/133

Abstract: Alternately skewed gates to reduce signal transmission delay. For one embodiment, an integrated circuit includes a chain of gates alternately skewed for fast rise and fast fall. Pulse encoding logic coupled to the chain of gates pulse encodes a signal to be provided to and transmitted by the chain of alternately skewed gates.

Abstract translation: 交替偏斜的门，以减少信号传输延迟。 对于一个实施例，集成电路包括交替地偏斜以便快速上升和快速下降的栅极链。 耦合到门链的脉冲编码逻辑脉冲编码将被提供给交替偏移门的链并由其传送的信号。

公开(公告)号：US5973510A

公开(公告)日：1999-10-26

申请号：US059685

申请日：1998-04-14

Applicant: Ya-Nan Mou

Inventor： Ya-Nan Mou

IPC: H03K19/0185 ,  H03K19/175

CPC classification number: H03K19/018521

Abstract: The input and output interface in the present invention can includes following components. A first circuit and a second circuit are placed. Means for switching a coupling between the two circuits is used. Grounding means is employed for setting the first terminal to a ground connection. Triggering means is used for triggering the grounding means and the switching means. The method for interfacing input and output between a first circuit and a second circuit includes the steps as follows. At first, an output disable signal of the first circuit is detected. Then a first terminal is isolated from a second terminal. The first terminal is an input and output terminal of the first circuit and the second terminal is an input and output terminal of the second circuit. Next, the first terminal is grounded. The first terminal is then floated. Finally, the first terminal and the second terminal is coupled for the first circuit to receive an output signal from the second circuit.

Abstract translation: 本发明的输入输出接口可包括以下部件。 放置第一电路和第二电路。 使用用于切换两个电路之间的耦合的装置。 接地装置用于将第一端子设置为接地连接。 触发装置用于触发接地装置和开关装置。 用于在第一电路和第二电路之间连接输入和输出的方法包括以下步骤。 首先，检测第一电路的输出禁止信号。 然后，第一终端与第二终端隔离。 第一端子是第一电路的输入和输出端子，第二端子是第二电路的输入和输出端子。 接下来，第一端子接地。 然后第一个终端浮动。 最后，第一端子和第二端子被耦合用于第一电路以接收来自第二电路的输出信号。

公开(公告)号：US08456188B2

公开(公告)日：2013-06-04

申请号：US12312352

申请日：2007-11-07

Applicant: Yasuhisa Nakajima ,  Hidekazu Kikuchi ,  Takehiko Saitou ,  Shigehiro Kawai ,  Masaki Kitano

Inventor： Yasuhisa Nakajima ,  Hidekazu Kikuchi ,  Takehiko Saitou ,  Shigehiro Kawai ,  Masaki Kitano

IPC: H03K19/175 ,  G06F13/38

CPC classification number: H04N21/43615 ,  H04N5/775 ,  H04N7/163 ,  H04N21/234309 ,  H04N21/4122 ,  H04N21/4135 ,  H04N21/43632 ,  H04N21/43635

Abstract: To discriminate whether a cable in conformity with a conventional standard or a cable in conformity with a new standard is connected.An HPD signal line (902) has, on an expanded HDMI sink apparatus (402) side circuit, a pull-up resistor (911) between the HPD signal line (902) and a voltage supply and a pull-down resistor (913) between the HPD signal line (902) and the ground, and a reserved line (903) has, on the expanded HDMI sink apparatus (402) side circuit, a pull-down resistor (914) between the reserved line (903) and a ground, and within a new HDMI cable (901), a pull-up resistor (912) between the reserved line (903) and a voltage supply of an expanded HDMI source apparatus (401). The expanded HDMI sink apparatus compares a voltage at a test point (19) on the reserved line (903) on the expanded HDMI sink apparatus (402) side with a reference voltage by using a voltage comparator (916). A CPU of the expanded HDMI sink apparatus (402) determines, when an output from the voltage comparator (916) is High, a normal state where the new HDMI cable (901) is inserted, and when an output from the voltage comparator (916) is Low, determines a state where a conventional HDMI cable (931) is erroneously inserted.

Abstract translation: 为了区分符合常规标准的电缆或符合新标准的电缆是否连接。 在扩展的HDMI宿设备（402）侧电路上，HPD信号线（902）在HPD信号线（902）和电压源和下拉电阻（913）之间具有上拉电阻（911） 在扩展的HDMI宿装置（402）侧电路之间，在保留线（903）和保护线（903）之间的下拉电阻（914）之间，在HPD信号线（902）和地之间， 接地，并且在新的HDMI电缆（901）内，在保留线（903）和扩展的HDMI源设备（401）的电压源之间的上拉电阻（912）。 扩展的HDMI宿设备通过使用电压比较器（916）将扩展的HDMI宿设备（402）侧的保留线路（903）上的测试点（19）处的电压与参考电压进行比较。 扩展的HDMI宿设备（402）的CPU当电压比较器（916）的输出为高时，确定插入新的HDMI电缆（901）的正常状态，并且当来自电压比较器（916）的输出 ）为低，确定传统HDMI电缆（931）错误插入的状态。

公开(公告)号：US07880501B2

公开(公告)日：2011-02-01

申请号：US12486176

申请日：2009-06-17

Applicant: Hee-Seok Han ,  Hyoung-Rae Kim

Inventor： Hee-Seok Han ,  Hyoung-Rae Kim

IPC: H03K19/175

CPC classification number: G09G3/3696 ,  G09G3/3648 ,  G09G2310/0289 ,  G09G2330/02 ,  H03K3/356113 ,  H03K19/018571

Abstract: Level shifting circuits generate multiple tracking signals that are in-phase with an input signal, but are also level-shifted with wider voltage swings relative to the input signal. These input tracking signals are provided as separate inputs to an inverter having at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein. A level shifting circuit may include a differential input circuit, which is responsive to true and complementary input signals. A first load circuit is electrically coupled to the differential input circuit. This first load circuit is configured to generate first and second tracking signals at respective first and second nodes therein. These first and second tracking signals are in-phase, level-shifted versions of each other, and have respective voltage swings that are greater than a voltage swing of the complementary input signals. The inverter includes a pull-up transistor responsive to the first tracking signal and a pull-down transistor responsive to the second tracking signal.

Abstract translation: 电平移位电路产生与输入信号同相的多个跟踪信号，但是也相对于输入信号具有更宽的电压摆幅而电平移位。 这些输入跟踪信号作为分离的输入提供给具有至少一个PMOS上拉晶体管和至少一个NMOS下拉晶体管的反相器。 电平移位电路可以包括差分输入电路，其响应于真实和互补的输入信号。 第一负载电路电耦合到差分输入电路。 该第一负载电路被配置为在其中的相应的第一和第二节点处产生第一和第二跟踪信号。 这些第一和第二跟踪信号是彼此的同相，电平移位版本，并且具有大于互补输入信号的电压摆幅的各自的电压摆幅。 反相器包括响应于第一跟踪信号的上拉晶体管和响应于第二跟踪信号的下拉晶体管。

公开(公告)号：US07242220B2

公开(公告)日：2007-07-10

申请号：US11062874

申请日：2005-02-23

Applicant: Shi-Hsiang Lu

Inventor： Shi-Hsiang Lu

IPC: H03K19/175

CPC classification number: H03K19/01721 ,  G09G3/3611 ,  H03K19/018521

Abstract: A signal transmitting system comprising a signal outputting unit and a signal receiving unit is provided. The signal outputting unit receives a first signal and outputs a second signal. The signal receiving unit receives the second signal and outputs a third signal. The signal outputting unit comprises an inverting device which receives the first signal and outputs a first inverted signal, and a signal driving device which receives the first inverted signal and outputs the second signal. The signal driving device comprises two NMOS transistors. The first NMOS transistor has a drain biased by a first voltage, and a gate receiving a control signal. The second NMOS transistor has a gate receiving the first inverted signal, a source biased by a second voltage, and a drain electronically coupled to the source of the first transistor. The drain of the second NMOS transistor outputs the second signal.

Abstract translation: 提供了包括信号输出单元和信号接收单元的信号发送系统。 信号输出单元接收第一信号并输出​​第二信号。 信号接收单元接收第二信号并输出​​第三信号。 信号输出单元包括接收第一信号并输出​​第一反相信号的反相装置，以及接收第一反相信号并输出​​第二信号的信号驱动装置。 信号驱动装置包括两个NMOS晶体管。 第一NMOS晶体管具有由第一电压偏置的漏极，并且栅极接收控制信号。 第二NMOS晶体管具有接收第一反相信号的栅极，由第二电压偏置的源极和电耦合到第一晶体管的源极的漏极。 第二NMOS晶体管的漏极输出第二信号。

公开(公告)号：US07215146B2

公开(公告)日：2007-05-08

申请号：US10977146

申请日：2004-10-29

Applicant: Naveed Khan

Inventor： Naveed Khan

IPC: H03K19/175

CPC classification number: H03K17/102 ,  H03K3/356113

Abstract: Embodiments of the invention include apparatus with a level-up shifter including a comparator having a pair of cross coupled PFETs with sources coupled to an I/O power supply and gates coupled to each other's drain, and a differential pair of NFETs with sources coupled to ground and gates respectively coupled to a data input and an inverted data input; and first and second pull-up PFETs have sources coupled to a pull-up voltage and drains respectively coupled between the differential pair of NFETs and the pair of cross coupled PFETs. The cross coupled PFETs and differential pair of NFETs perform level translation of low swing logic levels at the data input to high swing logic levels on a drain of one of the cross-coupled PFETs, while first and second pull-up PFETs speed the level translation in response to the data input and the inverted data input.

Abstract translation: 本发明的实施例包括具有电平转换移位器的装置，其具有比较器，该比较器具有耦合到I / O电源的源极和耦合到彼此漏极的栅极的一对交叉耦合PFET，以及耦合到 分别耦合到数据输入和反相数据输入的接地和门; 并且第一和第二上拉PFET具有耦合到分别耦合在差分对NFET和一对交叉耦合PFET之间的上拉电压和漏极的源极。 交叉耦合PFET和NFET的差分对在数据输入端执行低摆幅逻辑电平的电平转换，使得交叉耦合PFET之一的漏极上的高摆幅逻辑电平进行电平转换，而第一和第二上拉PFET加速电平转换 响应于数据输入和反相数据输入。

公开(公告)号：US07180330B2

公开(公告)日：2007-02-20

申请号：US10949251

申请日：2004-09-27

Applicant: Hiroki Kinugawa ,  Yoshinori Ishikawa

Inventor： Hiroki Kinugawa ,  Yoshinori Ishikawa

IPC: H03K19/175 ,  G05F1/10

CPC classification number: H03K17/063 ,  H03K17/0822

Abstract: An output circuit includes: a power supply unit; an output MIS transistor connected to the power supply unit; a reference MIS transistor that is connected to the power supply unit and is invariably in ON state; a current supply unit for generating a reference voltage Vref; an output terminal through which a current is supplied to a load circuit; a comparator; a logic circuit; and a control circuit for carrying out the ON/OFF control of the output MIS transistor. Comparison is made between the reference voltage Vref and output terminal voltage Vout by utilizing the ON-state resistances of the output and reference MIS transistors, thus detecting the magnitude of an output current. If the output current exceeds the target value, the output MIS transistor is turned OFF, thereby protecting it from an excessive current.

Abstract translation: 输出电路包括：电源单元; 连接到电源单元的输出MIS晶体管; 参考MIS晶体管，其连接到电源单元并且总是处于导通状态; 用于产生参考电压Vref的电流供应单元; 输出端子，电流被提供给负载电路; 比较器 一个逻辑电路; 以及用于执行输出MIS晶体管的ON / OFF控制的控制电路。 通过利用输出和参考MIS晶体管的导通电阻来比较参考电压Vref和输出端电压Vout，从而检测输出电流的大小。 如果输出电流超过目标值，则输出MIS晶体管截止，从而防止过电流。

公开(公告)号：US07151392B2

公开(公告)日：2006-12-19

申请号：US10977696

申请日：2004-10-29

Applicant: Sang Hee Lee

Inventor： Sang Hee Lee

IPC: H03K19/175

CPC classification number: G11C7/1057

Abstract: The present invention relates to an output driver circuit for a semiconductor memory device, in particular, a memory device using a DDR II concept or a concept similar thereto, which can reduce a variation in the slew rate of an output driver thereof between maximum and minimum values, while satisfying requirements of characteristics associated with slew rate.

Abstract translation: 本发明涉及一种用于半导体存储器件的输出驱动器电路，特别是涉及一种使用DDR II概念或类似于其的概念的存储器件，其可以将其输出驱动器的压摆率在最大和最小值之间的变化减小 值，同时满足与转换速率相关的特性要求。

公开(公告)号：US07091767B2

公开(公告)日：2006-08-15

申请号：US11041232

申请日：2005-01-25

Applicant: Kazuo Tanaka ,  Hiroyuki Mizuno ,  Rie Nishiyama ,  Manabu Miyamoto

Inventor： Kazuo Tanaka ,  Hiroyuki Mizuno ,  Rie Nishiyama ,  Manabu Miyamoto

IPC: H03L5/00 ,  H03K19/175

CPC classification number: H03K3/356113 ,  H01L2924/0002 ,  H03K3/356104 ,  H01L2924/00

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.