Abstract:
An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP1 amplifying a current signal Iin from a photodiode PD, and converting an amplified signal into a voltage signal; and an operating-point controller circuit VTCTL1 controlling an operation of the PREAMP1. The PREAMP1 includes a negative feedback path formed by a feedback resistance Rf1, and includes: a level-shift circuit LS1 level-shifting in accordance with an operating-point control signal Vcon; and an amplifier circuit AMP1 connected to a subsequent stage of the LS1 and performing an amplifying operation with a high gain. The VTCTL1 includes a replica circuit configured by the same circuit and circuit parameter as those of the AMP1 and electrically connected between the input and the output, and generates the Vcon so that an output DC level of this replica circuit is matched with an input DC level of the AMP1.
Abstract:
Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment, the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.
Abstract:
An optical receiver includes an optical detector that generates a photocurrent at an output. A transimpedance amplifier generates an amplified voltage signal corresponding to the photocurrent generated by the optical detector. An offset voltage generator generates an offset voltage that biases the voltage signal generated by the transimpedance amplifier. A switch having a first input electrically connected to the output of the transimpedance amplifier and a second input electrically connected to the output of the offset voltage generator switches between the offset voltage and the voltage signal generated by the transimpedance amplifier.
Abstract:
A signal amplifier circuit includes peak value holding circuit 11 receiving positive-phase input signal, peak value holding circuit 12 receiving negative-phase input signal, adder 13 adding the positive-phase input signal and output signal of peak value holding circuit 12, adder 14 adding the negative-phase input signal and output signal of the peak value holding circuit 11, non-inverting amplifier 15 amplifying output signal of adder 13, non-inverting amplifier 16 amplifying output signal of adder 14, peak value holding circuit 21 receiving positive-phase output signal of non-inverting amplifier 15, peak value holding circuit 22 receiving negative-phase output signal of non-inverting amplifier 16, adder 23 adding the positive-phase output signal and output signal of peak value holding circuit 22, adder 24 adding the negative-phase output signal and output signal of peak value holding circuit 21, and differential amplifier 29 amplifying difference between output signals of adders 23 and 24. Error in discrimination for small-amplitude signal embedded in tail is reduced.
Abstract translation:信号放大电路包括接收正相输入信号的峰值保持电路11,接收负相输入信号的峰值保持电路12,将正相输入信号和峰值保持电路12的输出信号相加的加法器13,加法器14 增加峰值保持电路11的负相输入信号和输出信号,放大加法器13的输出信号的非反相放大器15,放大加法器14的输出信号的非反相放大器16,接收正输出信号的峰值保持电路21, 非反相放大器15的相位输出信号,接收非反相放大器16的负相输出信号的峰值保持电路22,将正相输出信号和峰值保持电路22的输出信号相加的加法器23,加法器24相加 峰值保持电路21的负相输出信号和输出信号,放大加法器23a的输出信号之差 d 24.减少了嵌入尾部的小振幅信号的辨别误差。
Abstract:
A control device with a switchable bandwidth including: an integrating element with a first capacitance, which is charged and discharged by at least one current; at least one second capacitance, which can be connected in parallel with the first capacitance via a first switch; and at least one voltage follower, via which the voltage present at the first capacitance can be fed to the second capacitance. In this case, the first switch is open if the voltage present at the first capacitance is fed to the second capacitance by means of the voltage follower. The first switch is closed if the second capacitance is connected in parallel with the first capacitance. The invention enables a further capacitance to be supplementarily connected without a disturbance signal arising.
Abstract:
Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment, the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.
Abstract:
An optical receiver may include a photodetector that is configured to generate an electrical signal in response to detecting an optical signal, a first gain path coupled to receive and amplify the electrical signal generated by the photodetector, and a second gain path coupled to receive and amplify the electrical signal generated by the photodetector. The second gain path may have a higher gain than the first gain path. The two gain paths may be configured to amplify the electrical signal independently of each other. The optical receiver may also include a switch that selectably outputs an amplified electrical signal from one of the gain paths based on a magnitude of a signal corresponding to the optical signal.
Abstract:
A fiber optic receiver that includes an opto-electronic transducer, an adjustable response preamplifier circuit, and a post-amplifier circuit is described. The opto-electronic transducer is configured to generate an electrical data signal in response to a received optical data signal. The adjustable response preamplifier circuit is coupled to the opto-electronic transducer and is operable to amplify an electrical data signal generated by the opto-electronic transducer. The post-amplifier circuit is coupled to an output of the preamplifier circuit and is configured to transmit a mode control signal to the preamplifier circuit in response to a received control signal. By transmitting the mode control signal from the post-amplifier to the preamplifier, the adjustable response amplifier may be placed in the preamplifier stage within a receiver optical sub-assembly (ROSA). As a result, the fiber optic receiver may accommodate multiple operating modes (e.g., multiple bandwidth and power operating modes) while conforming to existing receiver optical sub-assembly (ROSA) size and pin count constraints.
Abstract:
A control device with a switchable bandwidth including: an integrating element with a first capacitance, which is charged and discharged by at least one current; at least one second capacitance, which can be connected in parallel with the first capacitance via a first switch; and at least one voltage follower, via which the voltage present at the first capacitance can be fed to the second capacitance. In this case, the first switch is open if the voltage present at the first capacitance is fed to the second capacitance by means of the voltage follower. The first switch is closed if the second capacitance is connected in parallel with the first capacitance. The invention enables a further capacitance to be supplementarily connected without a disturbance signal arising.
Abstract:
A burst signal detection circuit for detecting the arrival of a burst-like signal, which can accurately detect the burst signal against the DC level variations even in the case where the arriving burst signal is a weak signal, is disclosed. A DC variation removing circuit detects the bottom level of an input signal and removes the DC level variation of the input signal based on the bottom level. An amplitude identifying circuit detects the presence or absence of a burst signal based on the output signal of the DC variation removing circuit. The amplitude identifying circuit includes an amplitude detection circuit for detecting the maximum amplitude of the output signal of the DC variation removing circuit, a threshold level control circuit for controlling the threshold level and a comparator for comparing the output level of the amplitude detection circuit with the threshold level and outputting a detection signal indicating the presence or absence of a burst signal.