公开(公告)号：US20160079992A1

公开(公告)日：2016-03-17

申请号：US14857145

申请日：2015-09-17

Applicant: Intel Corporation

Inventor： Cho-Ying Lu ,  William Yee Li ,  Khoa Minh Nguyen ,  Ashoke Ravi ,  Maneesha Yellepeddi ,  Binta M. Patel

IPC: H03L7/099 ,  H03L7/08 ,  H03L1/00

CPC classification number: H03L7/085 ,  H03L1/00 ,  H03L7/08 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/0992 ,  H03L2207/50

Abstract: A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.

Abstract translation: 公开了一种用于分配表征和校准参数的系统。 该系统包括频率测量电路和有限状态机。 频率测量电路被配置为测量振荡信号的频率并产生包括测量频率的测量信号。 有限状态机被配置为通过频率测量电路来控制测量，基于测量信号为参数分配表征，并且基于所表征的参数来产生校准信号。

公开(公告)号：US09281779B2

公开(公告)日：2016-03-08

申请号：US14491037

申请日：2014-09-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Herschel A. Ainspan ,  Ram Kelkar ,  Anjali R. Malladi ,  Ramana M. Malladi

IPC: H03L1/00 ,  H03B5/04 ,  H03B5/12 ,  H03B7/02 ,  G06F17/50 ,  H03B7/06 ,  H03L7/04

CPC classification number: H03B5/1265 ,  G06F17/5045 ,  H03B5/04 ,  H03B5/1206 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03B7/02 ,  H03B7/06 ,  H03B2200/004 ,  H03B2200/005 ,  H03B2201/0208 ,  H03B2202/042 ,  H03L1/00 ,  H03L7/04

Abstract: Embodiments of the present invention provide a design structure and method for compensating for a change in frequency of oscillation (FOO) of an LC-tank VCO that includes a first node; second node; inductor; first capacitive network (FCN) that allows the design structure to obtain a target FOO; compensating capacitive (CCN) network that compensates for a change in the design structure's FOO; second capacitive network (SCN) that allows the design structure to obtain a desired FOO; a filter that supplies a voltage to the SCN and is coupled to the SCN; a transconductor that compensates for a change in the design structure's FOO; and a sub-circuit coupled to the SCN that generates and supplies voltage to the CCN sufficient to allow the CCN to compensate for a reduction in the design structure's FOO. The first and second nodes are coupled to the inductor, FCN, CCN, SCN, and sub-circuit.

Abstract translation: 本发明的实施例提供了一种用于补偿包括第一节点的LC槽VCO的振荡频率（FOO）变化的设计结构和方法; 第二节点 电感; 第一电容网络（FCN），允许设计结构获得目标FOO; 补偿电容（CCN）网络，补偿设计结构的FOO的变化; 第二电容网络（SCN），其允许设计结构获得期望的FOO; 一个向SCN提供电压并耦合到SCN的滤波器; 一种补偿设计结构FOO变化的跨导体; 以及耦合到SCN的子电路，其产生并向CCN提供足够的电压以允许CCN补偿设计结构的FOO的减少。 第一和第二节点耦合到电感器，FCN，CCN，SCN和子电路。

公开(公告)号：US20150338456A1

公开(公告)日：2015-11-26

申请号：US14816591

申请日：2015-08-03

Applicant: SK hynix Inc.

Inventor： Young Suk SEO ,  Ho Uk SONG ,  Jun Hyun CHUN ,  Tae Jin KANG

IPC: G01R31/26 ,  H03L7/06 ,  H03L1/00

CPC classification number: G01R31/2644 ,  G01R31/2607 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015 ,  G11C29/50012 ,  H03L1/00 ,  H03L7/06

Abstract: A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.

Abstract translation: 一种半导体装置，包括：输出定时控制器，被配置为将施加的外部读取命令延迟预定时间，并且在正常模式期间产生正常输出使能标志信号，所述测试输出定时控制器被配置为从外部产生DLL时钟信号 时钟信号，与DLL时钟信号同步地延迟施加的外部读取命令，并且在测试模式期间输出延迟的外部应用外部读取命令作为测试输出使能标志信号，以及多路复用器（MUX），其被配置为输出任何一个 正常输出使能标志信号或测试输出使能标志信号作为输出使能标志信号。

公开(公告)号：US09182779B1

公开(公告)日：2015-11-10

申请号：US14216395

申请日：2014-03-17

Applicant: Marvell International Ltd.

Inventor： Robert Mack ,  Timothy Chen

IPC: G06F1/02 ,  H03B28/00 ,  H03L1/00 ,  G06F1/03 ,  H03L7/099

CPC classification number: G06F1/022 ,  G06F1/0328 ,  G06F1/08 ,  H03B28/00 ,  H03B2200/0088 ,  H03L1/00 ,  H03L7/0994

Abstract: A method for compensating NCO jitter by changing a step value used to increment an accumulator in the NCO to make up for inaccuracies, or jitters. In one approach, a remainder in the accumulator may be monitored and a compensated clock close to the current edge of an ideal clock may be generated. In another approach, a compensated clock close to the next edge of the ideal clock may be generated after the current edge of the ideal clock is missed. The step value may be stored in a memory, which may be a register. A jitter compensator may include a comparator for monitoring the remainder in the accumulator or a detector for detecting whether an ideal clock has been missed. The jitter compensator may also change the step value to a step value for a faster clock to compensate jitter.

Abstract translation: 一种用于通过改变用于增加NCO中的累加器的步长值来补偿NCO抖动以补偿不准确或不稳定的方法。 在一种方法中，可以监视累加器中的余数，并且可以产生接近理想时钟的当前边缘的补偿时钟。 在另一种方法中，在理想时钟的当前边缘被错过之后，可以产生靠近理想时钟的下一个边缘的补偿时钟。 步数值可以存储在可以是寄存器的存储器中。 抖动补偿器可以包括用于监视累加器中的余数的比较器或用于检测是否错过理想时钟的检测器。 抖动补偿器还可以将步长值改变为更快时钟的步进值以补偿抖动。

公开(公告)号：US09148153B2

公开(公告)日：2015-09-29

申请号：US14143116

申请日：2013-12-30

Applicant: Intel Corporation

Inventor： Cho-Ying Lu ,  William Yee Li ,  Khoa Minh Nguyen ,  Ashoke Ravi ,  Maneesha Yellepeddi ,  Binta M. Patel

IPC: H03L7/06 ,  H03L1/00 ,  H03L7/099 ,  H03L7/08

CPC classification number: H03L7/085 ,  H03L1/00 ,  H03L7/08 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/0992 ,  H03L2207/50

Abstract: A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.

Abstract translation: 公开了一种用于分配表征和校准参数的系统。 该系统包括频率测量电路和有限状态机。 频率测量电路被配置为测量振荡信号的频率并产生包括测量频率的测量信号。 有限状态机被配置为通过频率测量电路来控制测量，基于测量信号为参数分配表征，并且基于所表征的参数来产生校准信号。

公开(公告)号：US20150256188A1

公开(公告)日：2015-09-10

申请号：US14635252

申请日：2015-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heechai KANG

IPC: H03L7/099 ,  H03L7/08

CPC classification number: H03L7/099 ,  H03L1/00 ,  H03L7/0802 ,  H03L7/093

Abstract: A phase-locked loop circuit includes a first circuit, a second circuit, and a voltage down converter. The first circuit generates a first signal based on a reference signal and a feedback signal, and operates based on a first supply voltage. The second circuit generates an oscillation signal based on a second signal, generates the feedback signal by dividing the oscillation signal, and operates based on a second supply voltage lower than the first supply voltage. The voltage down converter generates the second signal by decreasing an activation voltage level of the first signal. The voltage down converter includes at least one passive element electrically connected between the first circuit and the second circuit.

Abstract translation: 锁相环电路包括第一电路，第二电路和降压转换器。 第一电路基于参考信号和反馈信号产生第一信号，并且基于第一电源电压进行操作。 第二电路基于第二信号产生振荡信号，通过分频振荡信号产生反馈信号，并且基于低于第一电源电压的第二电源电压进行操作。 降压转换器通过降低第一信号的激活电压电平来产生第二信号。 所述降压转换器包括电连接在所述第一电路和所述第二电路之间的至少一个无源元件。

公开(公告)号：US20150244381A9

公开(公告)日：2015-08-27

申请号：US14231730

申请日：2014-03-31

Applicant: MoSys, Inc.

Inventor： Prashant Choudhary ,  Aldo Bottelli ,  Charles W. Boecker

IPC: H03L7/07

CPC classification number: H03L1/00 ,  H03L7/07 ,  H03L7/08 ,  H03L7/0816 ,  H04L7/0338

Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.

Abstract translation: 延迟锁定环路包括用于控制延迟锁定环路中的延迟元件的两个反馈回路。 第一反馈回路包括反馈电路，用于基于延迟锁定环路的输入时钟信号与由延迟锁定环路产生的输出时钟信号之间的相位差产生指示延迟调整的反馈信号。 第二反馈回路包括功率调节器，其通过使用反馈信号作为参考来调节电源来产生调节信号。 延迟锁定环路还包括包括电阻 - 电容网络的可变延迟电路。 可变延迟电路基于反馈信号控制电阻 - 电容网络中的电容，并根据调节信号控制电阻 - 电容网络的电阻。 以这种方式，可变延迟电路通过基于反馈信号和调节信号两者延迟输入时钟信号来产生输出时钟信号。

公开(公告)号：US09112514B2

公开(公告)日：2015-08-18

申请号：US14459291

申请日：2014-08-13

Applicant: IPGoal Microelectronics (Sichuan) Co., Ltd.

Inventor： Weihong Sun ,  Zhengxian Zou

IPC: H03K3/011 ,  H03K3/03 ,  H03L1/00 ,  H03L1/04

CPC classification number: H03L1/04 ,  H03K3/011 ,  H03K3/0322 ,  H03L1/00 ,  H03L1/022

Abstract: A high-precision oscillator includes a voltage reference module which includes multiple measured Field Effect Transistors and arranged for detecting process corners for the measured Field Effect Transistors to generate a reference voltage containing process corner information of the measured Field Effect Transistors, a compensation current generating module which is arranged for receiving the reference voltage, making a temperature compensation for the reference voltage, and generating a compensation current which includes both the process compensation and temperature compensation, and a ring oscillator which is arranged for receiving the compensation current and outputting a clock with stable frequency. The high-precision oscillator designs the process compensation and the temperature compensation separately, which are adjustable due to one of them will not be influenced by the other; and frequency of its outputted clock is not influenced by process and temperature, thereby precision of the outputted clock is improved.

Abstract translation: 高精度振荡器包括电压参考模块，其包括多个测量的场效应晶体管，并被布置用于检测所测量的场效应晶体管的处理角，以产生包含测量的场效应晶体管的过程角信息的参考电压，补偿电流产生模块 其布置用于接收参考电压，对参考电压进行温度补偿，并产生包括过程补偿和温度补偿的补偿电流，以及环形振荡器，其被布置为接收补偿电流并输出具有 稳定频率。 高精度振荡器分别设计过程补偿和温度补偿，由于其中的一个不会受另一个影响; 其输出时钟的频率不受过程和温度的影响，从而提高了输出时钟的精度。

公开(公告)号：US20150214958A1

公开(公告)日：2015-07-30

申请号：US14607789

申请日：2015-01-28

Applicant: MaxLinear, Inc.

Inventor： Sridhar Ramesh ,  Subramanian Anantharaman ,  Harish Maller

IPC: H03L7/00 ,  H03B5/30

CPC classification number: H03L7/00 ,  H03B5/1864 ,  H03L1/00

Abstract: Systems and methods are provided for detection and compensation of dielectric resonator oscillator frequency drift. DRO frequency drift detection and compensation may be applied in a system (e.g., outdoor unit) during handling of received signals. The DRO frequency drift detection and compensation may comprise, for each input signal, obtaining DRO frequency drift related information, related to the input signal; determining, based on the obtained DRO frequency drift related information, one or more adjustments applicable to processing of the input signal and/or the generation of the output signal using the at least portion of the input signal; and applying the one or more adjustments. The DRO frequency drift detection and compensation may be applied continually, occasionally, and/or periodically.

Abstract translation: 提供系统和方法用于介质谐振器振荡器频率漂移的检测和补偿。 在处理接收到的信号期间，DRO频率漂移检测和补偿可以应用于系统（例如，室外单元）中。 对于每个输入信号，DRO频率漂移检测和补偿可以包括与输入信号相关的DRO频率漂移相关信息; 基于所获得的DRO频率漂移相关信息，使用所述输入信号的所述至少一部分来确定适用于所述输入信号的处理和/或产生所述输出信号的一个或多个调整; 并应用一个或多个调整。 可以连续地，偶尔地和/或周期性地应用DRO频率漂移检测和补偿。

公开(公告)号：US09088290B2

公开(公告)日：2015-07-21

申请号：US14457802

申请日：2014-08-12

Applicant: IPGoal Microelectronics (Sichuan) Co., Ltd.

Inventor： Zhaolei Wu ,  Zhengxian Zou

IPC: H03B5/08 ,  H03L7/06 ,  H03B1/00 ,  H03L7/099

CPC classification number: H03L7/06 ,  H03B1/00 ,  H03L1/00 ,  H03L7/099

Abstract: An LC oscillator process compensation circuit includes an LC oscillator, a reference voltage terminal, a follower and a current auxiliary circuit, the LC oscillator includes a gain stage, an inductor and two voltage-controlled capacitors, the gain stage includes a first Field Effect Transistor, a second Field Effect Transistor, a third Field Effect Transistor and a fourth Field Effect Transistor, the current auxiliary circuit is connected with an external power source and the follower that connected with the reference voltage terminal to provide a working voltage for the LC oscillator, the follower includes a detection circuit to detecting current changes of the gain stage. The LC oscillator process compensation circuit has simple circuit structure and eliminates frequency changes of the LC oscillator caused by the process variations of the gain stage, thereby ensuring stability of the frequency of the LC oscillator, improving work precision and reducing design difficult.

Abstract translation: LC振荡器处理补偿电路包括LC振荡器，参考电压端子，跟随器和电流辅助电路，LC振荡器包括增益级，电感器和两个压控电容器，增益级包括第一场效应晶体管 ，第二场效应晶体管，第三场效应晶体管和第四场效应晶体管，当前辅助电路与外部电源连接，跟随器与参考电压端连接，为LC振荡器提供工作电压， 跟随器包括用于检测增益级的电流变化的检测电路。 LC振荡器工艺补偿电路具有简单的电路结构，消除了由增益级的工艺变化引起的LC振荡器的频率变化，从而确保了LC振荡器频率的稳定性，提高了工作精度，降低了设计难度。