公开(公告)号：US20050180203A1

公开(公告)日：2005-08-18

申请号：US10780171

申请日：2004-02-16

申请人： Wen-Chin Lin ,  Denny Tang ,  Li-Shyue Lai

发明人： Wen-Chin Lin ,  Denny Tang ,  Li-Shyue Lai

IPC分类号： G11C11/14 ,  G11C11/16

CPC分类号： G11C11/16 ,  G11C2213/72 ,  G11C2213/74

摘要： In one example, an MRAM memory array includes a plurality of word lines, a plurality of bit lines crossing the word lines, and a plurality of first and second diodes, and magnetic tunnel junction memories. Each first diode includes a cathode, and an anode coupled to each bit line. Each second diode includes an anode, and a cathode coupled to each word line. The magnetic tunnel junction memories include a pinned layer, a free layer, and a non-magnetic layer. The non-magnetic layer is located between the pinned layer and the free layer. Each diode is positioned at crossing points of the bit lines and the word lines and connected between the first diode at the corresponding crossing bit line and the second diode at the corresponding crossing word line.

摘要翻译： 在一个示例中，MRAM存储器阵列包括多个字线，与字线交叉的多个位线，以及多个第一和第二二极管以及磁性隧道结存储器。 每个第一二极管包括阴极和耦合到每个位线的阳极。 每个第二二极管包括阳极和耦合到每个字线的阴极。 磁性隧道结存储器包括钉扎层，自由层和非磁性层。 非磁性层位于被钉扎层和自由层之间。 每个二极管位于位线和字线的交叉点处，并连接在相应交叉位线处的第一二极管和相应交叉字线处的第二二极管之间。

公开(公告)号：US20090290410A1

公开(公告)日：2009-11-26

申请号：US12537093

申请日：2009-08-06

申请人： Yu-Jen Wang ,  Denny Tang ,  Hsu-Chen Cheng

发明人： Yu-Jen Wang ,  Denny Tang ,  Hsu-Chen Cheng

IPC分类号： G11C11/00 ,  G11C11/14

CPC分类号： H01L43/08 ,  G11C11/161 ,  G11C11/1675

摘要： The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area.

摘要翻译： 本公开提供了一种磁存储元件。 存储元件包括磁隧道结（MTJ）元件和电极。 电极包括钉扎层，钉扎层和非磁性导电层。 在一个实施例中，MTJ元件包括具有第一表面区域的第一表面，并且电极包括第二表面。 在该实施例中，电极的第二表面耦合到MTJ元件的第一表面，使得形成界面区域，并且界面面积小于第一表面积。

公开(公告)号：US20080291720A1

公开(公告)日：2008-11-27

申请号：US11752157

申请日：2007-05-22

申请人： Yu-Jen Wang ,  Denny Tang ,  Hsu-Chen Cheng

发明人： Yu-Jen Wang ,  Denny Tang ,  Hsu-Chen Cheng

IPC分类号： G11C11/15 ,  H01L21/00

CPC分类号： H01L43/08 ,  G11C11/161 ,  G11C11/1675

摘要： The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area.

摘要翻译： 本公开提供了一种磁存储元件。 存储元件包括磁隧道结（MTJ）元件和电极。 电极包括钉扎层，钉扎层和非磁性导电层。 在一个实施例中，MTJ元件包括具有第一表面区域的第一表面，并且电极包括第二表面。 在该实施例中，电极的第二表面耦合到MTJ元件的第一表面，使得形成界面区域，并且界面面积小于第一表面区域。

公开(公告)号：US20100118603A1

公开(公告)日：2010-05-13

申请号：US12687608

申请日：2010-01-14

申请人： Yu-Jen Wang ,  Hsu-Chen Cheng ,  Denny Tang

发明人： Yu-Jen Wang ,  Hsu-Chen Cheng ,  Denny Tang

IPC分类号： G11C11/14 ,  H01L29/82

CPC分类号： G11C11/1693 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675

摘要： The present disclosure provides a non-volatile memory device. A memory device includes a first magnetic element having a fixed magnetization. The memory device also includes a second magnetic element having a non-fixed magnetization. The memory device further includes a barrier layer between the first and second magnetic elements. A unidirectional current source is electrically coupled to the first and second magnetic elements. The current source is configured to provide a first current to the first and second memory elements. The first current has a first current density and is in a first direction. The current source is also configured to provide a second current to the first and second magnetic elements. The second current has a second current density, different than the first current density, and is in the first direction. The first and second currents cause the non-fixed magnetization of the second magnetic element to toggle between substantially parallel to the fixed magnetization of the first magnetic element and between substantially antiparallel to the fixed magnetization of the first magnetic element.

摘要翻译： 本公开提供了一种非易失性存储器件。 存储器件包括具有固定磁化强度的第一磁性元件。 存储器件还包括具有非固定磁化强度的第二磁性元件。 存储器件还包括在第一和第二磁性元件之间的阻挡层。 单向电流源电耦合到第一和第二磁性元件。 当前源被配置为向第一和第二存储器元件提供第一电流。 第一电流具有第一电流密度并且处于第一方向。 电流源还被配置为向第一和第二磁性元件提供第二电流。 第二电流具有与第一电流密度不同的第二电流密度，并且处于第一方向。 第一和第二电流导致第二磁性元件的非固定磁化在基本上平行于第一磁性元件的固定磁化之间以及基本上反平行于第一磁性元件的固定磁化之间翻转。

公开(公告)号：US20110059590A1

公开(公告)日：2011-03-10

申请号：US12945860

申请日：2010-11-14

申请人： Li-Shyue Lai ,  Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin

发明人： Li-Shyue Lai ,  Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin

IPC分类号： H01L21/02

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1691

摘要： A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.

摘要翻译： 一种相变存储器结构及其形成方法，所述方法包括提供包括导电区域的衬底; 在间隔物的上部形成具有部分暴露的侧壁区域的间隔物，其限定相变存储元件接触区域; 并且其中所述间隔件底部部分与所述导电区域重叠。 这两种方法都可以减少相变存储元件的有效面积，从而减少所需的相变电流。

公开(公告)号：US07858980B2

公开(公告)日：2010-12-28

申请号：US10791607

申请日：2004-03-01

申请人： Li-Shyue Lai ,  Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin

发明人： Li-Shyue Lai ,  Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin

IPC分类号： H01L29/18

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1691

摘要： A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.

摘要翻译： 一种相变存储器结构及其形成方法，所述方法包括提供包括导电区域的衬底; 在间隔物的上部形成具有部分暴露的侧壁区域的间隔物，其限定相变存储元件接触区域; 并且其中所述间隔件底部部分与所述导电区域重叠。 这两种方法都可以减少相变存储元件的有效面积，从而减少所需的相变电流。

公开(公告)号：US20080239794A1

公开(公告)日：2008-10-02

申请号：US11840051

申请日：2007-08-16

申请人： Wen-Chin Lin ,  Denny Tang ,  Hsu-Chen Cheng

发明人： Wen-Chin Lin ,  Denny Tang ,  Hsu-Chen Cheng

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to switch toggle-mode MRAM devices that employ a bias field to decrease the threshold needed to switch the magnetic state of each device. While the conventional toggle-mode write lines provide for the desired orthogonal orientation of the applied magnetic fields to optimize device switching, the use of a bias field affects this orthogonal orientation. By non-orthogonally aligning the two write lines as disclosed herein, the detrimental affect of the bias field may be compensated for such that the net fields applied to the device for both lines are again substantially orthogonal, as is desired.

摘要翻译： 这里公开了具有小角度切换写入线的触发模式磁阻随机存取存储器（MRAM）器件以及触发模式切换MRAM器件的相关方法。 还公开了根据所公开的原理构造的MRAM装置的布局。 一般来说，所公开的原理提供用于切换切换模式MRAM器件的非正交对准的触发模式写入线，其使用偏置场来降低切换每个器件的磁状态所需的阈值。 虽然常规的切换模式写入线提供所施加的磁场的期望的正交取向以优化器件切换，但偏置场的使用影响该正交取向。 如本文所公开的，通过非正交对准这两个写入线，可以补偿偏置场的有害影响，使得如所期望的那样，施加到两条线的器件的净场也基本正交。

公开(公告)号：US07417524B2

公开(公告)日：2008-08-26

申请号：US11353215

申请日：2006-02-13

申请人： Wai-Yi Lien ,  Denny Tang ,  Wen-Chin Lin ,  Chao-Hsiung Wang

发明人： Wai-Yi Lien ,  Denny Tang ,  Wen-Chin Lin ,  Chao-Hsiung Wang

IPC分类号： H01F5/00

CPC分类号： H01F17/0006 ,  H01F3/10 ,  H01F19/08 ,  H01F41/34 ,  H01F2017/0066 ,  H01F2017/0086

摘要： A semiconductor device having a semiconductor substrate and a first insulator overlying the semiconductor substrate. A spiral coil inductor overlies the first insulator and a second insulator overlies the spiral coil inductor. A patterned ferromagnetic film overlies the second insulator and a patterned magnetic-bias film overlies the patterned ferromagnetic film.

摘要翻译： 一种具有半导体衬底和覆盖半导体衬底的第一绝缘体的半导体器件。 螺旋线圈电感器覆盖在第一绝缘体上，第二绝缘体覆盖螺旋线圈电感器。 图案化的铁磁膜覆盖在第二绝缘体上，并且图案化的偏磁膜覆盖在图案化的铁磁膜上。

公开(公告)号：US07349243B2

公开(公告)日：2008-03-25

申请号：US11379527

申请日：2006-04-20

申请人： Wen-Chin Lin ,  Denny Tang ,  Hsu-Chen Cheng

发明人： Wen-Chin Lin ,  Denny Tang ,  Hsu-Chen Cheng

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： Disclosed herein are various embodiments of a 3-parameter switching technique for MRAM memory cells arranged on an MRAM array. The disclosed technique alters the relationship between the disturbance margin and write margin of MRAM arrays to reduce the overall disturbance for the arrays by either enlarging the write margin with respect to the original disturbance margin or enlarging the disturbance margin in view of the original write margin. In either approach, the disclosed 3-parameter switching technique successfully decreases the inadvertent writing of unselected bits.

摘要翻译： 这里公开了布置在MRAM阵列上的MRAM存储器单元的3参数切换技术的各种实施例。 所公开的技术改变MRAM阵列的扰动余量与写入余量之间的关系，以通过相对于原始干扰裕度放大写入裕度或者根据原始写入裕度来扩大扰动余量来减小阵列的整体干扰。 在任一方法中，所公开的3参数切换技术成功地减少了无选择位的无意写入。

公开(公告)号：US20070247900A1

公开(公告)日：2007-10-25

申请号：US11379527

申请日：2006-04-20

申请人： Wen-Chin Lin ,  Denny Tang ,  H.C. Cheng

发明人： Wen-Chin Lin ,  Denny Tang ,  H.C. Cheng

IPC分类号： G11C11/14

CPC分类号： G11C11/16

摘要： Disclosed herein are various embodiments of a 3-parameter switching technique for MRAM memory cells arranged on an MRAM array. The disclosed technique alters the relationship between the disturbance margin and write margin of MRAM arrays to reduce the overall disturbance for the arrays by either enlarging the write margin with respect to the original disturbance margin or enlarging the disturbance margin in view of the original write margin. In either approach, the disclosed 3-parameter switching technique successfully decreases the inadvertent writing of unselected bits.

摘要翻译： 这里公开了布置在MRAM阵列上的MRAM存储器单元的3参数切换技术的各种实施例。 所公开的技术改变MRAM阵列的扰动余量与写入余量之间的关系，以通过相对于原始干扰裕度放大写入裕度或者根据原始写入裕度来扩大扰动余量来减小阵列的整体干扰。 在任一方法中，所公开的3参数切换技术成功地减少了无选择位的无意写入。