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公开(公告)号：US20200073498A1
公开(公告)日：2020-03-05
申请号：US16303342
申请日：2018-09-11
Inventor： Yuehua Yang , Mang Zhao
Abstract: A touch panel and a display device are disclosed, the touch panel includes a touch unit array, a plurality of touch switches, a plurality of touch wires, and an integrated circuit board, the touch switches are connected to the touch wires, the touch wires connect the touch units to the touch switches, wherein each of the touch units is connected to at least two of the touch wires that evenly distributed within each of the touch units.
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公开(公告)号：US10403222B2
公开(公告)日：2019-09-03
申请号：US15790006
申请日：2017-10-22
Inventor： Mang Zhao
IPC: G09G3/36
Abstract: A gate driver on array (GOA) circuit includes a plurality of stages of GOA units cascaded. A first control latch module, a signal processing module, and a second control latch module of an Nth stage GOA unit generate an Nth stage dipulse gate driving signal and an Nth stage cascade signal according to clock signals, and an (N−2)th or (N+2)th stage cascade signal. For the clock signals corresponding to adjacent two stages of the GOA units, a first clock signal is delayed for a predetermined period of time with respect to a second clock signal. The two dipulse gate driving signals generated by the adjacent two stages of the GOA units partially overlap.
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公开(公告)号：US10360869B2
公开(公告)日：2019-07-23
申请号：US15564121
申请日：2017-05-03
Inventor： Mang Zhao
IPC: G09G3/36 , G02F1/1368 , G02F1/1362 , H01L27/12
Abstract: A liquid crystal panel driving circuit and a liquid crystal display device are provided. Every three sub-pixel unit columns are defined as a row cycle that comprises a first data line, a second data line, and a third data line coupled to a same data driving signal output line of the data driver via the switch unit. The switch unit is configured to control the first data line, the second data line, and the third data line to output data signals in different output orders.
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公开(公告)号：US10042223B2
公开(公告)日：2018-08-07
申请号：US14888971
申请日：2015-07-31
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd
Inventor： Mang Zhao , Yong Tian , Caiqin Chen
IPC: H02H9/00 , G02F1/1362 , G09G3/36 , G02F1/1368 , H01L27/12 , H01L27/02 , H02H9/04
Abstract: The present disclosure relates to an array substrate, a display panel and a display device. The array substrate includes GND wirings and GOA areas. The GND wirings are configured at outer sides of the GOA areas, and the GOA area includes a variety of GOA signal lines and N-th stage GOA circuits electrically connected by the GOA signal lines. A first ESD protection circuit is configured in a middle area between the 1-th stage GOA circuit and the N-th stage GOA circuit to discharge abnormal electrical charges of the GOA signal lines within the middle area. With such configuration, better ESD protection capability is provided between the GOA signal lines.
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公开(公告)号：US10032425B2
公开(公告)日：2018-07-24
申请号：US15119385
申请日：2016-05-25
Inventor： Shijuan Yi , Mang Zhao
Abstract: The CMOS GOA circuit of reducing clock signal loading comprises the input control module (1), the latch module (2), the reset module (3), the signal process module (4) and the output buffer module (5); in the input control module (1), the clock signal (CK(M)) merely needs to control the second N type thin film transistor and the fifth N type thin film transistor (T2, T5), and the amount of the thin film transistors driven by the clock signal can be decreased to reduce the clock signal loading, and to lower the RC delay and the power consumption of the clock signal; the latch module (2) utilizes the inverted scan drive signal (XGate(N−2)) of the two former N-2th stage GOA unit to be the input control signal of the stage transfer signal Q(N) to solve the competition problem occurs as the stage transfer signal (Q(N)) is inputted.
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Patent Agency Ranking
公开(公告)号：US09997125B2
公开(公告)日：2018-06-12
申请号：US15802981
申请日：2017-11-03
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng Xiao , Mang Zhao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2300/0408 , G09G2310/0251 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2330/04
Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.
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公开(公告)号：US09972283B2
公开(公告)日：2018-05-15
申请号：US15024075
申请日：2016-02-22
Inventor： Mang Zhao
IPC: G09G3/3266 , G09G5/18
CPC classification number: G09G5/18 , G09G3/20 , G09G3/3266 , G09G3/3674 , G09G2300/0426 , G09G2310/0267 , G09G2310/0281 , G09G2310/08 , G09G2330/021
Abstract: The present disclosure relates to scanning driving circuit and flat display device. A pull-up maintaining module receives clock signals at the previous level, to charge a pull-up control signal node and pull up a pull-down control signal node; a control module receives pull-up control signals at the previous level and scanning driving signals at the previous level, and control the pull-up maintaining module; an output module connects to the pull-up maintaining module and the control module for outputting the scanning driving signals to scanning lines; the scanning lines transmits the scanning driving signals to pixel cells.
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公开(公告)号：US09959832B2
公开(公告)日：2018-05-01
申请号：US15802951
申请日：2017-11-03
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng Xiao , Mang Zhao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2300/0408 , G09G2310/0251 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2330/04
Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.
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公开(公告)号：US09953606B2
公开(公告)日：2018-04-24
申请号：US15802924
申请日：2017-11-03
Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng Xiao , Mang Zhao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2300/0408 , G09G2310/0251 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2330/04
Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.
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公开(公告)号：US09935127B2
公开(公告)日：2018-04-03
申请号：US14783870
申请日：2015-08-21
IPC: H01L29/417 , H01L27/12 , H01L29/786 , H01L27/092 , H03K5/135 , H01L27/32
CPC classification number: H01L27/1222 , H01L27/092 , H01L27/1225 , H01L27/124 , H01L27/1248 , H01L29/41733 , H01L29/78603 , H01L29/78606 , H01L29/78633 , H01L29/78648 , H01L29/78675 , H03K5/135
Abstract: A control circuit of a thin film transistor, comprising: a substrate; a silicon nitride layer disposed on the substrate; a silicon dioxide layer disposed on the silicon nitride layer; a light shielding layer disposed inside the silicon nitride layer, which comprising a first light shielding region and a second light shielding region; at least one N type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the first light shielding region; at least one P type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the second light shielding region; each of the N type metal oxide semiconductor and the P type metal oxide semiconductor has a gate electrode layer, a first control signal received by voltage pulses of the gate electrode layer synchronized with a second control signal received by the light shielding layer in voltage variation.
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