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公开(公告)号：US10658365B2
公开(公告)日：2020-05-19
申请号：US16052636
申请日：2018-08-02
Inventor： Li-Wei Feng , Shih-Fang Tzou , Chien-Cheng Tsai , Chih-Chi Cheng , Chia-Wei Wu , Ger-Pin Lin
IPC: H01L27/108
Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
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公开(公告)号：US10529719B2
公开(公告)日：2020-01-07
申请号：US15961827
申请日：2018-04-24
Inventor： Po-Han Wu , Li-Wei Feng , Shih-Han Hung , Fu-Che Lee , Chien-Cheng Tsai
IPC: H01L27/108 , H01L21/768
Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.
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公开(公告)号：US20190206982A1
公开(公告)日：2019-07-04
申请号：US16297733
申请日：2019-03-11
Inventor： Tzu-Chin Wu , Wei-Hsin Liu , Yi-Wei Chen , Chia-Lung Chang , Jui-Min Lee , Po-Chun Chen , Li-Wei Feng , Ying-Chiao Wang , Wen-Chieh Lu , Chien-Ting Ho , Tsung-Ying Tsai , Kai-Ping Chen
IPC: H01L49/02 , H01L27/108 , H01L29/94
Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
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公开(公告)号：US10290736B2
公开(公告)日：2019-05-14
申请号：US15872996
申请日：2018-01-17
Inventor： Kai-Ping Chen , Li-Wei Feng , Kuei-Hsuan Yu , Chiu-Hsien Yeh
IPC: H01L29/78 , H01L29/423 , H01L27/108
Abstract: A semiconductor device and a method of forming the same are provided. A substrate is provided. A trench is formed in the substrate and a conductive material is formed filling the trench. A portion of the conductive material filling an upper portion of the trench is removed to expose an upper surface of the substrate and an upper corner and an upper sidewall of the trench. A doping process is performed to form a doped region in the substrate along the exposed upper surface of the substrate and the exposed upper corner and upper sidewall of the trench. The doped region has an upside-down L shape.
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公开(公告)号：US10236294B2
公开(公告)日：2019-03-19
申请号：US15854827
申请日：2017-12-27
Inventor： Chien-Ting Ho , Shih-Fang Tzou , Chun-Yuan Wu , Li-Wei Feng , Yu-Chieh Lin , Ying-Chiao Wang , Tsung-Ying Tsai
IPC: H01L27/105 , H01L21/768 , H01L21/02 , H01L29/66 , H01L21/311 , H01L21/3105
Abstract: The present invention proposes a method of manufacturing a semiconductor device, which includes the steps of providing a substrate with a memory region and a logic region, forming bit lines and logic gates respectively in the memory region and the logic region, wherein storage node regions are defined between bit lines, forming a first low-K dielectric layer on sidewalls of bit lines, forming a doped silicon layer in the storage node regions between bit lines, wherein the top surface of doped silicon layer is lower than the top surface of bit line, forming a second low-K dielectric layer on sidewalls of storage node regions, and filling up storage node regions with metal plugs.
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Patent Agency Ranking
公开(公告)号：US20180301458A1
公开(公告)日：2018-10-18
申请号：US15922899
申请日：2018-03-15
Inventor： Pin-Hong Chen , Tsun-Min Cheng , Chih-Chieh Tsai , Tzu-Chieh Chen , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Yi-Wei Chen , Hsin-Fu Huang , Chi-Mao Hsu , Li-Wei Feng , Ying-Chiao Wang , Chung-Yen Feng
IPC: H01L27/108 , H01L23/532 , H01L23/522 , H01L21/285 , H01L23/528 , H01L21/768
Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
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公开(公告)号：US20180286966A1
公开(公告)日：2018-10-04
申请号：US15995083
申请日：2018-05-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Li-Wei Feng , Shih-Hung Tsai , Chih-Kai Hsu , Jyh-Shyang Jenq
IPC: H01L29/66 , H01L29/78 , H01L21/308
CPC classification number: H01L29/66545 , H01L21/3085 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/6681 , H01L29/785
Abstract: A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed between the two sub regions. A recess is disposed in each sub region. A semiconductor layer is formed to fill the recesses. A patterned mask layer is formed on the semiconductor layer in the sub regions and on the substrate in the dummy region. The substrate and the semiconductor layer are removed by using the patterned mask layer as a mask, thereby forming a plurality of fin structures in the sub regions and a plurality of dummy fin structures in the dummy region.
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公开(公告)号：US20180277546A1
公开(公告)日：2018-09-27
申请号：US15915026
申请日：2018-03-07
Inventor： Ying-Chiao Wang , Li-Wei Feng , Chien-Ting Ho , Tsung-Ying Tsai
IPC: H01L27/108 , H01L29/06 , H01L21/762
CPC classification number: H01L27/10894 , H01L21/76224 , H01L27/10805 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10897 , H01L29/0649
Abstract: A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a plurality of bit lines, a gate, a spacer layer and a first spacer. The substrate has a memory cell region and a periphery region, the a plurality of bit lines are disposed on the substrate, within the memory cell region, and the gate is disposed on the substrate, within the periphery. The spacer layer covers the bit lines and a sidewall of the gate. The first spacer is disposed at two sides of the gate, covers on the spacer layer.
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公开(公告)号：US10068907B1
公开(公告)日：2018-09-04
申请号：US15593338
申请日：2017-05-12
Inventor： Tsung-Ying Tsai , Chien-Ting Ho , Ming-Te Wei , Li-Wei Feng , Ying-Chiao Wang
IPC: H01L23/528 , H01L27/108 , H01L29/06
Abstract: A dynamic random access memory (DRAM) includes a substrate, two buried word lines and a bit line contact. The substrate includes a first active area, wherein the first active area extends along a first direction. The buried word lines are disposed in the substrate and across the first active area, wherein the buried word lines extend along a second direction. The bit line contact is disposed on the substrate and overlaps the first active area between the two buried word lines, wherein the bit line contact is enclosed by a first side, a second side, a third side and a fourth side, and the first side is parallel to the third side along a third direction while the second side is parallel to the fourth side along a fourth direction, wherein the third direction is parallel to the first direction and the fourth direction is parallel to the second direction.
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公开(公告)号：US20180190656A1
公开(公告)日：2018-07-05
申请号：US15854827
申请日：2017-12-27
Inventor： Chien-Ting Ho , Shih-Fang Tzou , Chun-Yuan Wu , Li-Wei Feng , Yu-Chieh Lin , Ying-Chiao Wang , Tsung-Ying Tsai
IPC: H01L27/105 , H01L21/768 , H01L21/02 , H01L29/66 , H01L21/311
CPC classification number: H01L27/1052 , H01L21/02532 , H01L21/31053 , H01L21/31111 , H01L21/76834 , H01L21/76846 , H01L21/76879 , H01L21/76895 , H01L21/76897 , H01L27/1085 , H01L27/10894 , H01L29/6653 , H01L29/6656
Abstract: The present invention proposes a method of manufacturing a semiconductor device, which includes the steps of providing a substrate with a memory region and a logic region, forming bit lines and logic gates respectively in the memory region and the logic region, wherein storage node regions are defined between bit lines, forming a first low-K dielectric layer on sidewalls of bit lines, forming a doped silicon layer in the storage node regions between bit lines, wherein the top surface of doped silicon layer is lower than the top surface of bit line, forming a second low-K dielectric layer on sidewalls of storage node regions, and filling up storage node regions with metal plugs.
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