公开(公告)号：US20240411334A1

公开(公告)日：2024-12-12

申请号：US18331620

申请日：2023-06-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chen-Ming Hung ,  Chung-Cheng Chou

IPC: G05F1/59 ,  G11C11/16 ,  G11C13/00

Abstract: A circuit includes a memory macro comprising a plurality of memory banks. The circuit includes a first voltage regulator configured to provide a first operation voltage to the memory macro at a first output node. The circuit includes a second voltage regulator configured to provide a second operation voltage to the memory macro at a second output node. The second operation voltage is substantially higher than the first operation voltage. The circuit includes a decoupling capacitor configured to be alternately shared by the first voltage regulator when the memory macro receives the first operation voltage, and by the second voltage regulator when the memory macro receives the second operation voltage.

公开(公告)号：US12027205B2

公开(公告)日：2024-07-02

申请号：US17828979

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0033 ,  G11C2213/79

Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.

公开(公告)号：US12014776B2

公开(公告)日：2024-06-18

申请号：US17856811

申请日：2022-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chung-Cheng Chou ,  Hsu-Shun Chen ,  Chien-An Lai ,  Pei-Ling Tseng ,  Zheng-Jun Lin

IPC: G11C13/00

CPC classification number: G11C13/0038 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

Abstract: A memory circuit includes a bias voltage generator including a bias voltage node, an activation voltage generator including a resistive device, and a first amplifier, a drive circuit including a second amplifier including an input terminal coupled to the bias voltage node, and a resistive random-access memory (RRAM) array. The activation voltage generator and the first amplifier are configured to generate a portion of a bias voltage level on the bias voltage node based on a resistance of the resistive device, and the drive circuit is configured to output a drive voltage having the bias voltage level to the RRAM array.

公开(公告)号：US11837287B2

公开(公告)日：2023-12-05

申请号：US17825566

申请日：2022-05-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Pei-Ling Tseng

IPC: G11C13/00 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12

CPC classification number: G11C13/004 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C2013/0042

Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.

公开(公告)号：US20230207005A1

公开(公告)日：2023-06-29

申请号：US17828979

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0033 ,  G11C2213/79

Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.

公开(公告)号：US10930344B2

公开(公告)日：2021-02-23

申请号：US16422924

申请日：2019-05-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chung-Cheng Chou ,  Hsu-Shun Chen ,  Chien-An Lai ,  Pei-Ling Tseng ,  Zheng-Jun Lin

IPC: G11C13/00

Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first current path configured to receive a first current from a current source, and output a bias voltage based on a voltage difference generated from conduction of the first current in the first current path. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to conduct a second current responsive to the drive voltage.