公开(公告)号：US20240221858A1

公开(公告)日：2024-07-04

申请号：US18608220

申请日：2024-03-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC: G11C29/42 ,  G11C29/20 ,  G11C29/24 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/20 ,  G11C29/24 ,  G11C29/44

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.

公开(公告)号：US11984164B2

公开(公告)日：2024-05-14

申请号：US18300706

申请日：2023-04-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Perng-Fei Yuh ,  Yih Wang ,  Ku-Feng Lin ,  Jui-Che Tsai ,  Hiroki Noguchi ,  Fu-An Wu

IPC: G11C14/00 ,  G11C11/16 ,  G11C11/419

CPC classification number: G11C14/0081 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/419

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

公开(公告)号：US11935610B2

公开(公告)日：2024-03-19

申请号：US17856756

申请日：2022-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC: G11C29/20 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/20 ,  G11C29/24 ,  G11C29/44

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.

公开(公告)号：US20240038281A1

公开(公告)日：2024-02-01

申请号：US18447904

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Jui-Che Tsai ,  Perng-Fei Yuh ,  Yih Wang

IPC: G11C7/06 ,  H01L27/06 ,  H03K3/037 ,  H03K3/356

CPC classification number: G11C7/065 ,  H01L27/0629 ,  H03K3/037 ,  H03K3/35613

Abstract: A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.

公开(公告)号：US11854650B2

公开(公告)日：2023-12-26

申请号：US18084570

申请日：2022-12-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin

IPC: G11C7/06

CPC classification number: G11C7/06

Abstract: A memory device that includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. A first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. The gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. Each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage.

公开(公告)号：US20230260557A1

公开(公告)日：2023-08-17

申请号：US17669628

申请日：2022-02-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Ku-Feng Lin

IPC: G11C7/10 ,  G11C7/06 ,  G11C8/08

CPC classification number: G11C7/1012 ,  G11C7/1063 ,  G11C7/109 ,  G11C7/1096 ,  G11C7/06 ,  G11C8/08

Abstract: A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.

公开(公告)号：US11601117B1

公开(公告)日：2023-03-07

申请号：US17407451

申请日：2021-08-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Jui-Che Tsai ,  Perng-Fei Yuh ,  Yih Wang

IPC: G11C7/06 ,  H03K3/356 ,  H03K3/037 ,  H01L27/06

Abstract: A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.

公开(公告)号：US20220293141A1

公开(公告)日：2022-09-15

申请号：US17829333

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Yu-Der Chih

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/12

Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.

公开(公告)号：US20220254386A1

公开(公告)日：2022-08-11

申请号：US17731248

申请日：2022-04-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC: G11C7/06

Abstract: A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.

公开(公告)号：US20220157351A1

公开(公告)日：2022-05-19

申请号：US17096966

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Yu-Der Chih

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/08

Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.