公开(公告)号：US10923175B2

公开(公告)日：2021-02-16

申请号：US16230185

申请日：2018-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US10916279B2

公开(公告)日：2021-02-09

申请号：US16848364

申请日：2020-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hoon Son ,  Si-Hong Kim ,  Chang-Kyo Lee ,  Jung-Hwan Choi ,  Kyung-Soo Ha

IPC: G11C7/24 ,  H03H7/38 ,  G11C7/10

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

公开(公告)号：US10566038B2

公开(公告)日：2020-02-18

申请号：US15918526

申请日：2018-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hoon Son ,  Si-Hong Kim ,  Chang-Kyo Lee ,  Jung-Hwan Choi ,  Kyung-Soo Ha

IPC: G11C7/10 ,  G11C7/24 ,  H03H7/38

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

公开(公告)号：US10535394B2

公开(公告)日：2020-01-14

申请号：US16039404

申请日：2018-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hwa Kim ,  Tae-Young Oh ,  Jin-Hun Jang ,  Kyung-Soo Ha

IPC: G11C11/4074

Abstract: A memory device includes a first switch for switching a first power voltage and transmitting the first power voltage to a common node of a first power rail. A second switch switches a second power voltage and transmits the second power voltage to the common node. A control logic generates a first control signal for controlling the first switch during initial driving of the memory device. A masking circuit controls the first switch to maintain a turn on state in at least a partial period of the initial driving period of the memory device by providing a first masking control signal obtained by masking the first control signal to the first switch.

公开(公告)号：US09424897B2

公开(公告)日：2016-08-23

申请号：US14165990

申请日：2014-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Hyun Kim ,  Seung-Jun Bae ,  Kyung-Soo Ha

IPC: G11C7/22 ,  H03K19/003 ,  G11C7/10 ,  H03K19/094

CPC classification number: G11C7/22 ,  G11C7/1048 ,  G11C7/1057 ,  H03K19/00361 ,  H03K19/09429

Abstract: Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal.

Abstract translation: 提供了一种均衡器和包括该均衡器的半导体存储器件。 均衡器包括延迟电路和反相电路。 延迟电路被配置为响应于选择信号输出延迟施加到输入/输出节点的输入信号的延迟信号和反相输入信号的反相信号之一。 反相电路被配置为反转从延迟电路提供的信号并将反相信号输出到输入/输出节点。 均衡器被配置为使得当延迟电路输出延迟信号时，均衡器作为放大输入信号并输出​​放大的输入信号的感应偏置电路工作，并且当延迟电路输出反相信号时，均衡器作为锁存器 电路存储和输出输入信号。

公开(公告)号：US09397661B2

公开(公告)日：2016-07-19

申请号：US14742219

申请日：2015-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Soo Ha

IPC: H03K19/0185 ,  H03K19/00 ,  H03K19/003

CPC classification number: H03K19/0005 ,  H03K19/00369

Abstract: An ODT circuit capable of generating an OCD/ODT code and/or a reference voltage adaptively adjusted according to a system environment is disclosed. The ODT circuit comprises a system environment detector, an OCD/ODT replica circuit, an OCD/ODT code generator and an OCD/ODT unit. The system environment detector detects a supply voltage to generate a voltage code, detects an operating temperature to generate a temperature code, and detects an operating frequency to generate a frequency code. The OCD/ODT code generator generates a pull-up code and a pull-down code currently optimized for a semiconductor memory device based on a pull-up reference voltage, a pull-down reference voltage, the voltage code, the temperature code and the frequency code.

Abstract translation: 公开了能够产生根据系统环境自适应调整的OCD / ODT码和/或参考电压的ODT电路。 ODT电路包括系统环境检测器，OCD / ODT复制电路，OCD / ODT码发生器和OCD / ODT单元。 系统环境检测器检测电源电压以产生电压代码，检测工作温度以产生温度代码，并检测工作频率以产生频率代码。 OCD / ODT代码生成器根据上拉参考电压，下拉参考电压，电压代码，温度代码和对于半导体存储器件的下拉代码生成当前针对半导体存储器件优化的上拉代码和下拉代码 频码