公开(公告)号：US20240256452A1

公开(公告)日：2024-08-01

申请号：US18339488

申请日：2023-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Suk Han Lee ,  Kyomin Sohn

IPC: G06F12/0811 ,  G06F12/0891

CPC classification number: G06F12/0811 ,  G06F12/0891

Abstract: Disclosed is a semiconductor memory device and a memory system, including at least one high-bandwidth memory device configured to store data or output stored data according to an access command, a processor configured to generate the access command for the high-bandwidth memory device, and a logic die on the high-bandwidth memory device and including a last level cache providing a cache function to the processor. The last level cache is configured to perform a cache bypassing operation to directly access the high-bandwidth memory device without a cache replacement operation when an invalid line and a clean line do not exist in a cache miss state in response to a cache read or cache write request by the processor.

公开(公告)号：US20240178861A1

公开(公告)日：2024-05-30

申请号：US18339490

申请日：2023-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho Kim ,  Seongmuk Kang ,  Daehyun Kim ,  Kijun Lee ,  Myungkyu Lee ,  Kyomin Sohn ,  Sunghye Cho

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1111 ,  H03M13/611

Abstract: A memory controller to control a memory module including a plurality of data chips, a first parity chip and a second parity chip, includes a system error correction code (ECC) engine and a processor to control the system ECC engine. The system ECC engine includes an ECC decoder and a memory to store a parity check matrix. The ECC decoder selects one of a plurality of ECC decoding schemes based on decoding status flags and corrects a plurality of symbol errors in a read codeword set from the memory module by performing an ECC decoding on the read codeword set based on the selected decoding scheme and the parity check matrix. The decoding status flags are provided from the plurality of data chips and each of the decoding status flags indicates whether at least one error bit is detected in respective one of the plurality of data chips.

公开(公告)号：US20240096391A1

公开(公告)日：2024-03-21

申请号：US18341128

申请日：2023-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghye Cho ,  Kijun Lee ,  Eunae Lee ,  Kyomin Sohn ,  Yeonggeol Song ,  Myungkyu Lee

IPC: G11C11/406

CPC classification number: G11C11/406

Abstract: A memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer managing circuit, which is configured to detect a row hammer address based on a pre row hammer address, and each of a plurality of input row addresses associated with a plurality of accesses during a monitoring period for monitoring the plurality of accesses to a plurality of the rows of memory cells. A refresh control circuit is provided and is configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address.

公开(公告)号：US20230352084A1

公开(公告)日：2023-11-02

申请号：US18157035

申请日：2023-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijun Lee ,  Youngmin Kang ,  Ikjoon Chang ,  Kyomin Sohn

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/419

Abstract: A storage circuit includes a multi-stage latch circuit having first to fourth transistor pairs therein, which respectively include a pull-up transistor and a pull-down transistor connected in series through a corresponding one of first to fourth storage nodes. An access circuit is provided, which has a plurality of access transistors of different conductivity type therein. The access transistors are electrically coupled to at least two of the first to fourth storage nodes and configured to enable writing of data bits into at least some of the first to fourth storage nodes, and reading of data bits from at least some of the first to fourth storage nodes. A control circuit is provided, which controls the access circuit during the writing and reading.

公开(公告)号：US11664061B2

公开(公告)日：2023-05-30

申请号：US17722494

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Sanghyuk Kwon ,  Kyomin Sohn ,  Jaeyoun Youn ,  Haesuk Lee

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/406 ,  G11C11/4085

Abstract: A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.

公开(公告)号：US11567692B2

公开(公告)日：2023-01-31

申请号：US17213732

申请日：2021-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongil O ,  Jongpil Son ,  Kyomin Sohn

IPC: G06F3/06

Abstract: A memory device including an interface circuit for data conversion according to different endian formats includes an interface circuit that performs data conversion with hardware in a data transfer path inside the memory device in accordance with a memory bank, a processing element (PE), and an endian format of a host device. The interface circuit is (i) between a memory physical layer interface (PHY) region and a serializer/deserializer (SERDES) region, (ii) between the SERDES region and the memory bank or the PE, (iii) between the SERDES region and a bank group input/output line coupled to a bank group including a number of memory banks, and (iv) between the PE and bank local input/output lines coupled to the memory bank.

公开(公告)号：US20220318164A1

公开(公告)日：2022-10-06

申请号：US17685987

申请日：2022-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyuk KWON ,  Nam Sung Kim ,  Kyomin Sohn ,  Jaeyoun Youn

IPC: G06F13/16 ,  H01L25/065

Abstract: A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

公开(公告)号：US20210407577A1

公开(公告)日：2021-12-30

申请号：US17475479

申请日：2021-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/406 ,  G11C8/12 ,  G11C11/4076

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.

公开(公告)号：US20210263671A1

公开(公告)日：2021-08-26

申请号：US17009992

申请日：2020-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Kyomin Sohn

IPC: G06F3/06 ,  H01L25/065

Abstract: A stacked memory device includes a plurality memory semiconductor dies, a plurality of through silicon vias, a function-in-memory (FIM) front-end circuit and a plurality of FIM back-end circuits. The buffer semiconductor die is configured to communicate with a host device. The memory semiconductor dies are stacked on the buffer semiconductor die, and include a plurality of memory banks. The through-silicon vias electrically connect the buffer semiconductor die and the memory semiconductor dies. The FIM front-end circuit receives a plurality of FIM instructions for a FIM operation from the host device, and stores the FIM instructions. The FIM operation includes data processing based on internal data read from the memory banks. The FIM back-end circuits are respectively included in the memory semiconductor dies. The FIM back-end circuits perform the FIM operation corresponding to the plurality of FIM instructions stored in the FIM front-end circuit under control of the FIM front-end circuit.

公开(公告)号：US20210134345A1

公开(公告)日：2021-05-06

申请号：US16903055

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Sanghyuk Kwon ,  Kyomin Sohn ,  Jaeyoun Youn ,  Haesuk Lee

IPC: G11C11/406 ,  G11C11/408

Abstract: A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.