公开(公告)号：US20220149153A1

公开(公告)日：2022-05-12

申请号：US17587444

申请日：2022-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-Jung KIM ,  Kyu Jin KIM ,  Sang-Il HAN ,  Kyu Hyun LEE ,  Woo Young CHOI ,  Yoo Sang HWANG

IPC: H01L29/06 ,  H01L29/423

Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

公开(公告)号：US20220093796A1

公开(公告)日：2022-03-24

申请号：US17542969

申请日：2021-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyujin KIM ,  Hui-Jung KIM ,  Junsoo KIM ,  Sangho LEE ,  Jae-Hwan CHO ,  Yoosang HWANG

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/311 ,  H01L27/108 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234

Abstract: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.

公开(公告)号：US20190164985A1

公开(公告)日：2019-05-30

申请号：US16027887

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Junsoo KIM ,  Hui-Jung KIM ,  Bong-Soo KIM ,  Satoru YAMADA ,  Kyupil LEE ,  Sunghee HAN ,  HyeongSun HONG ,  Yoosang HWANG

IPC: H01L27/11556 ,  H01L23/532 ,  H01L27/11524 ,  H01L49/02 ,  G11C8/14 ,  G11C7/18

Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.