公开(公告)号：US20220255579A1

公开(公告)日：2022-08-11

申请号：US17616539

申请日：2020-06-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA ,  Hitoshi KUNITAKE

IPC: H04B1/44 ,  H03K17/16 ,  H03K17/693

Abstract: A communication device capable of transmitting and receiving high-potential signals is provided. The communication device includes a duplexer including first to fourth transistors, a transmission terminal, a reception terminal, an antenna terminal, and first and second control terminals. The transmission terminal is electrically connected to one of a source and a drain of each of the first and second transistors. The reception terminal is electrically connected to one of a source and a drain of each of the third and fourth transistors. The antenna terminal is electrically connected to the other of the source and the drain of each of the second and fourth transistors. The first control terminal is electrically connected to gates of the second and third transistors. The second control terminal is electrically connected to gates of the first and fourth transistors. A semiconductor of each of the first to fourth transistors contains a metal oxide.

公开(公告)号：US20220208794A1

公开(公告)日：2022-06-30

申请号：US17606533

申请日：2020-04-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Kazuaki OHSHIMA ,  Kazuki TSUDA ,  Tomoaki ATSUMI

IPC: H01L27/12 ,  H01L27/108 ,  H01L29/786

Abstract: A semiconductor device with a small characteristic variation due to operating temperature is provided. The semiconductor device includes an odd number of stages of inverter circuits that are circularly connected. The inverter circuit includes a first transistor and a second transistor. A gate of the first transistor is electrically connected to one of a source and a drain of the first transistor, the one of the source and the drain of the first transistor is supplied with a high power supply potential, and the other of the source and the drain of the first transistor is electrically connected to an output terminal out. A gate of the second transistor is electrically connected to an input terminal in, one of a source and a drain of the second transistor is electrically connected to the output terminal out, and the other of the source and the drain of the second transistor is supplied with a low power supply potential. The first transistor and the second transistor include an oxide semiconductor in a semiconductor layer. The first transistor and the second transistor each include a back gate.

公开(公告)号：US20180122336A1

公开(公告)日：2018-05-03

申请号：US15792235

申请日：2017-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Yoshiyuki KUROKAWA

IPC: G09G5/10

CPC classification number: G09G5/10 ,  G02F1/133553 ,  G02F1/133603 ,  G02F1/13439 ,  G02F1/1368 ,  G02F2201/123 ,  G02F2201/44 ,  G09G3/2096 ,  G09G3/3413 ,  G09G3/3426 ,  G09G2300/0404 ,  G09G2300/0456 ,  G09G2310/08 ,  G09G2320/0646 ,  G09G2330/021 ,  G09G2360/12 ,  G09G2370/10 ,  G09G2370/16 ,  H01L27/1225 ,  H01L27/3232 ,  H01L27/3244 ,  H01L29/78651 ,  H01L29/7869

Abstract: A method for transmitting image data to a display device at high speed is provided. Image data to be transmitted is input to a phase modulation portion, and is mixed with a high-frequency carrier wave. The carrier wave is modulated with a technique of phase-shift keying, and output to a transmission line determined in consideration of the transmission characteristics of the high-frequency wave. A phase regulating portion of the phase modulation portion has a function of adjusting the amount of change in phase with the use of an electric signal. A phase demodulation portion beyond the transmission line demodulates the modulated carrier wave and extracts the image data. The multi-bit image data can be transmitted by the technique of the phase-shift keying. The high-speed transmission enables serial conversion of the original image data and decreases the number of transmission lines.

公开(公告)号：US20250159935A1

公开(公告)日：2025-05-15

申请号：US18835109

申请日：2023-01-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO

IPC: H10D30/67 ,  G11C5/06 ,  H10B12/00

Abstract: A storage device that can be miniaturized or highly integrated is provided. A storage device includes a memory cell including a transistor and a capacitor, a first insulator, a second insulator over the first insulator, and a third insulator over the second insulator. The transistor includes an oxide over the first insulator, a first conductor and a second conductor over the oxide, a fourth insulator over the oxide, and a third conductor over the fourth insulator. The second insulator includes a first opening. The fourth insulator and the third conductor are placed in the first opening. The second insulator and the third insulator each include a second opening. The capacitor includes a fourth conductor in contact with the top surface of the second conductor, a fifth insulator over the fourth conductor, and a fifth conductor over the fifth insulator. The second insulator includes a third opening. The first insulator includes a fourth opening. The third insulator includes a fifth opening. The third opening overlaps with at least part of the fourth opening and at least part of the fifth opening in a plan view. A sixth conductor and part of the first conductor are placed inside the third opening. The sixth conductor includes a region in contact with part of the top surface and part of a side surface of the first conductor.

公开(公告)号：US20250151294A1

公开(公告)日：2025-05-08

申请号：US18834280

申请日：2023-02-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Hitoshi KUNITAKE

IPC: H10B80/00 ,  H01L25/07 ,  H10B12/00 ,  H10D1/68

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. A storage device includes a first transistor, a second transistor, a first capacitor, and a second capacitor. The first capacitor includes a first electrode and a second electrode. The second capacitor includes the first electrode and a third electrode. One of a source and a drain of the first transistor is electrically connected to the second electrode; one of a source and a drain of the second transistor is electrically connected to the third electrode; and the first electrode includes a portion overlapping with each of the second electrode, the third electrode, the first transistor, and the second transistor and is supplied with a fixed potential or a ground potential.

公开(公告)号：US20250151254A1

公开(公告)日：2025-05-08

申请号：US18838009

申请日：2023-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO

IPC: H10B12/00

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a memory cell including first to third transistors and a capacitor. The second and third transistors share a metal oxide. The capacitor is provided between the first and second transistors. An insulator is provided over an electrode functioning as a source or a drain of the first transistor, and the insulator has an opening reaching the electrode. The capacitor is provided in the opening. One electrode of the capacitor includes, in the opening, a region in contact with the other of the source electrode and the drain electrode of the first transistor. The one electrode of the capacitor includes a region in contact with a gate electrode of the second transistor.

公开(公告)号：US20250131949A1

公开(公告)日：2025-04-24

申请号：US18832322

申请日：2023-01-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO

IPC: G11C5/10

Abstract: A novel storage device is provided. A storage device in which N memory layers each including a plurality of memory cells provided in a matrix (Nis an integer greater than or equal to 2) are stacked is provided. A write bit line, a read bit line, and a selection line are provided along a stacking direction of the memory layers, and a write word line and a read word line are provided in the direction orthogonal to the stacking direction of the memory layers. The memory cell includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to the write bit line through a first conductor including a region functioning as one of a source electrode and a drain electrode. The first conductor includes a region where at least one of the top surface, a side surface, and the bottom surface of the first conductor is in contact with the write bit line.

公开(公告)号：US20250120177A1

公开(公告)日：2025-04-10

申请号：US18924689

申请日：2024-10-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Tatsuya ONUKI ,  Hajime KIMURA ,  Takayuki IKEDA ,  Shunpei YAMAZAKI

IPC: H10D86/40 ,  H10D30/67

Abstract: A semiconductor device that occupies a small area is provided. The semiconductor device includes a first transistor including a first oxide semiconductor; a second transistor including a second oxide semiconductor; a capacitor element; a first insulator; and a first conductor in contact with a source or a drain of the second transistor. The capacitor element includes a second conductor, a third conductor, and a second insulator. The first transistor, the second transistor, and the first conductor are placed to be embedded in the first insulator. The second conductor is placed in contact with a top surface of the first conductor and a top surface of a gate of the first transistor. The second insulator is placed over the second conductor and the first insulator. The third conductor is placed to cover the second conductor with the second insulator therebetween.

公开(公告)号：US20250040193A1

公开(公告)日：2025-01-30

申请号：US18716572

申请日：2022-11-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hitoshi KUNITAKE ,  Satoru SAITO ,  Masahiro TAKAHASHI ,  Naoki OKUNO ,  Masashi OOTA

IPC: H01L29/786 ,  H01L21/324 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/792 ,  H10B12/00 ,  H10B43/20 ,  H10B80/00

Abstract: A semiconductor device with a high on-state current is provided. A transistor included in the semiconductor device includes a first insulator; a first semiconductor layer over the first insulator; a second semiconductor layer including a channel formation region over the first semiconductor layer; a first conductor and a second conductor over the second semiconductor layer; a second insulator over the second semiconductor layer and between the first conductor and the second conductor; and a third conductor over the second insulator. In a cross-sectional view in a channel width direction of the transistor, the third conductor covers a side surface and a top surface of the second semiconductor layer. The second semiconductor layer has a higher permittivity than the first semiconductor layer. In the cross-sectional view in the channel width direction of the transistor, a length of an interface between the first semiconductor layer and the second semiconductor layer is greater than or equal to 1 nm and less than or equal to 20 nm, and a length from a bottom surface of the second semiconductor layer to a bottom surface of the third conductor in a region not overlapping with the second semiconductor layer is larger than a thickness of the second semiconductor layer.

公开(公告)号：US20250031415A1

公开(公告)日：2025-01-23

申请号：US18715890

申请日：2022-11-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hitoshi KUNITAKE ,  Ryota HODO ,  Tatsuya ONUKI

IPC: H01L29/786 ,  H01L27/02 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first transistor including a first oxide, a second transistor including a second oxide, and a third oxide. The first oxide includes a channel formation region of the first transistor. The second oxide includes a channel formation region of the second transistor. The third oxide contains the same material as the first oxide and the second oxide. The third oxide is separated from the first oxide and the second oxide. In a top view, the third oxide is positioned between the first oxide and the second oxide. The third oxide is placed in the same layer as the first oxide and the second oxide.