公开(公告)号：US20240284657A1

公开(公告)日：2024-08-22

申请号：US18529698

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minho CHOI ,  Kiseok LEE ,  Chansic YOON ,  Chulkwon PARK ,  Jaybok CHOI

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor device includes a substrate having a plurality of active regions and defining a plurality of first gate trenches and a plurality of second gate trenches crossing the plurality of active regions and extending in a first horizontal direction, a plurality of gate structures including a plurality of first gate structures within the plurality of first gate trenches and a plurality of second gate structures within the plurality of second gate trenches, a bit line structure crossing the plurality of gate structures and extending in a second horizontal direction that intersects the first horizontal direction, and a contact plug disposed on a side surface of the bit line structure. When viewed in plan view, an area of at least some of the plurality of first gate structures is different from an area of at least some of the plurality of second gate structures.

公开(公告)号：US20240268123A1

公开(公告)日：2024-08-08

申请号：US18370207

申请日：2023-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Jinwoo HAN ,  Hanjin LIM

IPC: H10B53/30 ,  H10B53/40

CPC classification number: H10B53/30 ,  H10B53/40

Abstract: A semiconductor device includes gate structure, bit line structure, contact plug structure, stack structure, and capacitor. The gate structure is disposed on first substrate. The bit line structure is disposed on the gate structure. The contact plug structure is disposed on the first substrate and spaced apart from the bit line structure. The stack structure is disposed on the bit line structure and the contact plug structure, and may include insulation layers and plate electrodes alternately stacked in a vertical direction substantially perpendicular to an upper surface of the first substrate. The capacitor includes a second electrode extending through the stack structure and contacting the contact plug structure. A ferroelectric pattern is disposed on a sidewall of the second electrode. First electrodes are disposed on a sidewall of the ferroelectric pattern, contact sidewalls of the plate electrodes, respectively, and are spaced apart from each other in the vertical direction.

公开(公告)号：US20240268101A1

公开(公告)日：2024-08-08

申请号：US18471900

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： SangJae PARK ,  Seung-Bo KO ,  Keunnam KIM ,  Jongmin KIM ,  Hui-Jung KIM ,  Taejin PARK ,  Chan-Sic YOON ,  Kiseok LEE ,  Myeong-Dong LEE ,  Hongjun LEE

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/05 ,  H10B12/34 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor device includes first and second active patterns extending in a first direction and being adjacent to each other in a second direction, the first and second active patterns, each of which includes first and second edges spaced apart from each other in the first direction, a first storage node pad and a first storage node contact sequentially provided on the first edge of the first active pattern, a second storage node pad and a second storage node contact sequentially provided on the second edge of the second active pattern, and a fence pattern between the first and the second storage node contacts. Bottom and top surfaces of the first storage node contact are located at first and second levels, respectively. In a third direction, a width of the fence pattern at the first level is less than a width of the fence pattern at the second level.

公开(公告)号：US20240006250A1

公开(公告)日：2024-01-04

申请号：US18150324

申请日：2023-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunnam KIM ,  Kiseok LEE ,  Byeongjoo KU

IPC: H01L21/66 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L22/20 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76879 ,  H01L21/76816

Abstract: Disclosed is a semiconductor fabrication method comprising forming a first conductive structure and a second conductive structure, measuring a misalignment value between the first conductive structure and the second conductive structure, based on the measured misalignment value selecting a reticle from a set of reticles, and using the selected reticle to form a connection conductive structure that electrically connects the first conductive structure to the second conductive structure.

公开(公告)号：US20230157003A1

公开(公告)日：2023-05-18

申请号：US17828298

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Yongseok KIM ,  Hui-Jung KIM ,  Min Hee CHO ,  Yoosang HWANG

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10873 ,  H01L27/10897

Abstract: A semiconductor memory device including a stack structure including layer groups that are vertically stacked on a substrate and including a word line, a channel layer, and a data storage element that is electrically connected to the channel layer; and a vertically extending bit line on one side of the stack structure, wherein the word line of each of the layer groups extends in a first direction parallel to a top surface of the substrate, the layer groups include first and second layer groups that are sequentially stacked, the channel layer is below the word line of the first layer group, the channel layer is above the word line of the second layer group, and the bit line includes a first protrusion portion connected to the channel layer of the first layer group; and a second protrusion portion connected to the channel layer of the second layer group.

公开(公告)号：US20230157002A1

公开(公告)日：2023-05-18

申请号：US17745960

申请日：2022-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10897 ,  H01L27/10873

Abstract: A semiconductor memory device including a stack including layer groups vertically stacked on a substrate, each of the layer groups including a word line, a lower channel layer, an upper channel layer, and a data storing element electrically connected to the lower channel layer and the upper channel layer; and a bit line at a side of the stack, the bit line extending vertically, wherein the bit line includes a protruding portion connected to the lower channel layer and the upper channel layer of each layer group, the word line of each layer group extends in a first direction parallel to a top surface of the substrate, and the word line of each layer group is sandwiched between the lower channel layer and the upper channel layer of the layer group.

公开(公告)号：US20230084388A1

公开(公告)日：2023-03-16

申请号：US17730279

申请日：2022-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Min Hee CHO

IPC: H01L29/786 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, the channel layer including an amorphous oxide semiconductor, and a width of the gate electrode being greater than a width of the channel layer, a first conductive electrode connected to a first side surface of the channel layer, and a second conductive electrode connected to a second side surface of the channel layer.

公开(公告)号：US20230055147A1

公开(公告)日：2023-02-23

申请号：US17741701

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Wonsok LEE ,  Min Hee CHO

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, a word line extending in a second direction perpendicular to the first direction, a channel pattern between the bit line and the word line, the channel pattern including a horizontal channel portion, which is connected to the bit line, and a vertical channel portion, which is extended from the horizontal channel portion in a third direction perpendicular to the first and second directions, and a gate insulating pattern between the word line and the channel pattern. The horizontal channel portion of the channel pattern may be disposed parallel to a fourth direction that is inclined to the first and second directions.

公开(公告)号：US20230009575A1

公开(公告)日：2023-01-12

申请号：US17690371

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee CHO ,  Mintae RYU ,  Sungwon YOO ,  Wonsok LEE ,  Hyunmog PARK ,  Kiseok LEE

IPC: H01L29/786

Abstract: A semiconductor device including a conductive line on a substrate, a first gate electrode on the conductive line, a second gate electrode separated by a gate isolation insulating layer on the first gate electrode, a first channel layer on a side surface of the first gate electrode, with a first gate insulating layer therebetween, a first source/drain region on another side surface of the first gate electrode, a second channel layer on another side surface of the second gate electrode on a side that is opposite to the first channel layer, with a second gate insulating layer therebetween, a second source/drain region on the second channel layer, and a third source/drain region on the first channel layer and on a side surface of the second gate electrode on a same side as the first channel layer may be provided.

公开(公告)号：US20220328492A1

公开(公告)日：2022-10-13

申请号：US17847861

申请日：2022-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu LEE ,  Kiseok LEE ,  Woobin SONG ,  Minhee CHO

IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4094

Abstract: A semiconductor memory device includes a memory cell array of a three-dimensional structure including a plurality of memory cells repeatedly arranged in a first horizontal direction and a second horizontal direction that are parallel with a main surface of a substrate and cross each other on the substrate and in a vertical direction perpendicular to the main surface, wherein each of the plurality of memory cells includes three transistors. A method of manufacturing a semiconductor memory device includes forming simultaneously a plurality of memory cells arranged in a row in a vertical direction on a substrate, wherein each of the plurality of memory cells includes three transistors.