公开(公告)号：US11201193B2

公开(公告)日：2021-12-14

申请号：US16752288

申请日：2020-01-24

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao

IPC: H01L27/24 ,  H01L45/00

Abstract: Certain aspects of the present disclosure generally relate to a vertically stacked multilayer resistive random access memory (RRAM) and methods for fabricating such an RRAM. The vertically stacked multilayer RRAM generally includes a planar substrate layer and a plurality of metal-insulator-metal (MIM) stacks, each MIM stack structure of the plurality of MIM stacks comprising a plurality of MIM structures extending orthogonally above the planar substrate.

公开(公告)号：US20210351095A1

公开(公告)日：2021-11-11

申请号：US16868147

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

Abstract: Before a semiconductor die of a brittle compound semiconductor is encapsulated with a molding compound during package fabrication, side surfaces of the semiconductor die are treated to avoid or prevent surface imperfections from propagating and fracturing the crystal structure of the substrate of the III-V compound semiconductor under the stresses applied as the molding compound solidifies. Surfaces are treated to form a passivation layer, which may be a passivated layer of the substrate or a passivation material on the substrate. In a passivated layer, imperfections of an external layer are transformed to be less susceptible to fracture. Passivation material, such as a poly-crystalline layer on the substrate surface, diffuses stresses that are applied by the molding compound. Semiconductor dies in flip-chip and wire-bond chip packages with treated side surfaces as disclosed have a reduced incidence of failure caused by die fracturing.

公开(公告)号：US10971615B2

公开(公告)日：2021-04-06

申请号：US16058388

申请日：2018-08-08

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/06 ,  H01L29/66

Abstract: Certain aspects of the present disclosure provide a high electron mobility transistor (HEMT). The HEMT generally includes a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer disposed above the GaN layer. The HEMT also includes a source electrode, a gate electrode, and a drain electrode disposed above the AlGaN layer. The HEMT further includes n-doped protuberance(s) disposed above the AlGaN layer and disposed between at least one of: the gate electrode and the drain electrode; or the source electrode and the gate electrode. Each of the n-doped protuberances is separated from the gate electrode, the drain electrode, and the source electrode.

公开(公告)号：US10896981B1

公开(公告)日：2021-01-19

申请号：US16511093

申请日：2019-07-15

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Xia Li ,  Bin Yang

IPC: H01L29/93 ,  H01L29/66 ,  H01L29/778

Abstract: Aspects generally relate to a P-N junction varactor that can be integrated with high electron mobility transistor (HEMT) in a single device or die. The varactor and HEMT are fabricated with the same materials forming various layers of the varactor and HEMT. Using the same material stack-up to form the varactor and HEMT can reduce the number of processing steps during the fabrication of the integrated varactor and HEMT device. The integrated varactor and HEMT device may be used for RF circuits, such as radio frequency front end (RFFE) devices for use in 5G.

公开(公告)号：US10756206B2

公开(公告)日：2020-08-25

申请号：US15645188

申请日：2017-07-10

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao ,  Periannan Chidambaram

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L29/205 ,  H01L21/74 ,  H01L23/66 ,  H01L29/08 ,  H03F3/24 ,  H03F3/189 ,  H04W88/02

Abstract: A compound semiconductor field effect transistor may include a channel layer. The compound semiconductor transistor may also include a multi-layer epitaxial barrier layer on the channel layer. The channel layer may be on a doped buffer layer or on a first un-doped buffer layer. The compound semiconductor field effect transistor may further include a gate. The gate may be on a first tier of the multi-layer epitaxial barrier layer, and through a space between portions of a second tier of the multi-layer epitaxial barrier layer.

公开(公告)号：US10749017B1

公开(公告)日：2020-08-18

申请号：US16274094

申请日：2019-02-12

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10

Abstract: Power amplifiers in radio frequency circuits are typically implemented as heterojunction bipolar transistors. In applications such as in 5G systems, the circuits are expected to operate at very high speeds, e.g., up to 100 GHz. Also, a certain amount of output power should be maintained for stable operation. To achieve both high power and high speed, it is proposed to incorporate field plates in the heterojunction bipolar transistors to reduce electric field in the collector. This allows the breakdown voltage of the transistor to be high, which aids in power output. At the same time, the collector can be relatively thin, which aids in operation speed.

公开(公告)号：US20200075753A1

公开(公告)日：2020-03-05

申请号：US16116685

申请日：2018-08-29

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Gengming Tao ,  Xia Li

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/08 ,  H01L29/205 ,  H01L29/66 ,  H01L21/768

Abstract: Low resistance source/drain regions in III-V transistors are disclosed. More particularly, a source and a drain are formed from heavily doped III-V materials that have lower resistances than a barrier layer and/or a cap layer under the drain. In an exemplary aspect, the barrier and cap layers are formed over a mobility channel layer and then etched to form source and drain recesses. A source and a drain are then epitaxially grown in the recesses. The source and the drain may include one or more layers, with the top layer having the lowest bandgap, thus helping to lower contact resistance. By lowering the resistance of the source and the drain, the overall resistance of the transistor may be lowered to allow for operation at higher frequencies.

公开(公告)号：US10522367B2

公开(公告)日：2019-12-31

申请号：US15450605

申请日：2017-03-06

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L21/265 ,  H01L21/322 ,  H01L21/02 ,  H01L23/29 ,  H01L23/31

Abstract: An integrated circuit (IC) device may include a substrate having an active device layer. The integrated circuit may also include a first defect layer. The first defect layer may have a first surface facing a backside of the active device layer. The integrated circuit may further include a second defect layer. The second defect layer may face a second surface opposite the first surface of the first defect layer.

公开(公告)号：US10483287B1

公开(公告)日：2019-11-19

申请号：US16138084

申请日：2018-09-21

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/08

Abstract: Transistors formed on semiconductor substrates are not well-suited for integrated circuits employed in media designed to structurally flex to conform to a shaped surface or in response to physical stress. Structural flexing of wearable electronic devices, such as clothing, may cause cracking in the semiconductor substrate, resulting in failure of the integrated circuits. TFTs formed on flexible substrates can withstand structural flexing without failure. CMOS circuits are employed due to cost, performance, and power efficiency considerations. To provide increased drive strength for such applications, a flexible TFT structure for a CMOS circuit disclosed herein includes an exemplary NFET integrated with a complementary PFET on a flexible substrate. By forming a top gate on a semiconductor layer of a FET opposite to a bottom gate formed between the semiconductor layer and the flexible substrate, an effective thickness of an inversion channel layer induced in the semiconductor layer is doubled.

公开(公告)号：US10431581B1

公开(公告)日：2019-10-01

申请号：US15966225

申请日：2018-04-30

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Gengming Tao ,  Bin Yang

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/205 ,  H01L29/225 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/737

Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a substrate, a well region disposed adjacent to the substrate, a first fin disposed above the well region, a second fin disposed above the substrate, and a gate region disposed adjacent to each of the first fin and the second fin. The semiconductor device may also include at least one third fin disposed above the substrate, a support layer disposed above the at least one third fin, and a compound semiconductor device disposed above the support layer.