公开(公告)号：US10176090B2

公开(公告)日：2019-01-08

申请号：US15266765

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Natarajan Vaidhyanathan ,  Mattheus Cornelis Antonius Adrianus Heddes

IPC: G06F12/02 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0875 ,  H04L29/06 ,  H04L12/811

Abstract: Providing memory bandwidth compression using adaptive compression in central processing unit (CPU)-based systems is disclosed. In one aspect, a compressed memory controller (CMC) is configured to implement two compression mechanisms: a first compression mechanism for compressing small amounts of data (e.g., a single memory line), and a second compression mechanism for compressing large amounts of data (e.g., multiple associated memory lines). When performing a memory write operation using write data that includes multiple associated memory lines, the CMC compresses each of the memory lines separately using the first compression mechanism, and also compresses the memory lines together using the second compression mechanism. If the result of the second compression is smaller than the result of the first compression, the CMC stores the second compression result in the system memory. Otherwise, the first compression result is stored.

公开(公告)号：US10146693B2

公开(公告)日：2018-12-04

申请号：US15718449

申请日：2017-09-28

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Mark Anthony Rinaldi ,  Natarajan Vaidhyanathan

IPC: G06F12/04 ,  G06F12/12 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0862

Abstract: Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some aspects, a compressed memory controller (CMC) provides an LLC comprising multiple LLC lines, each providing a plurality of sub-lines the same size as a system cache line. The contents of the system cache line(s) stored within a single LLC line are compressed and stored in system memory within the memory sub-line region corresponding to the LLC line. A master table stores information indicating how the compressed data for an LLC line is stored in system memory by storing an offset value and a length value for each sub-line within each LLC line. By compressing multiple system cache lines together and storing compressed data in a space normally allocated to multiple uncompressed system lines, the CMC enables compression sizes to be smaller than the memory read/write granularity of the system memory.

公开(公告)号：US10067706B2

公开(公告)日：2018-09-04

申请号：US15086882

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Natarajan Vaidhyanathan

IPC: G06F12/08 ,  G06F12/10 ,  G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0875 ,  H03M7/30 ,  H03M13/00 ,  G06F12/0862 ,  G06F12/12

CPC classification number: G06F3/0638 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/0223 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/403 ,  G06F2212/466 ,  H03M7/30 ,  H03M13/6312 ,  Y02D10/13

Abstract: Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system is disclosed. In this regard, a compressed memory controller provides a CI hint directory comprising a plurality of CI hint directory entries, each providing a plurality of CI hints. The compressed memory controller is configured to receive a memory read request comprising a physical address of a memory line, and initiate a memory read transaction comprising a requested read length value. The compressed memory controller is further configured to, in parallel with initiating the memory read transaction, determine whether the physical address corresponds to a CI hint directory entry in the CI hint directory. If so, the compressed memory controller reads a CI hint from the CI hint directory entry of the CI hint directory, and modifies the requested read length value of the memory read transaction based on the CI hint.

公开(公告)号：US20180081579A1

公开(公告)日：2018-03-22

申请号：US15272951

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Carl Alan Waldspurger ,  Natarajan Vaidhyanathan ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Koustav Bhattacharya

IPC: G06F3/06 ,  G06F12/0891

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0685 ,  G06F12/0802 ,  G06F12/0891 ,  G06F13/1668 ,  G06F13/1694 ,  G06F2212/20 ,  G06F2212/60

Abstract: Providing flexible management of heterogeneous memory systems using spatial Quality of Service (QoS) tagging in processor-based systems is disclosed. In one aspect, a heterogeneous memory system of a processor-based system includes a first memory and a second memory. The heterogeneous memory system is divided into a plurality of memory regions, each associated with a QoS identifier (QoSID), which may be set and updated by software. A memory controller of the heterogeneous memory system provides a QoS policy table, which operates to associate each QoSID with a QoS policy state, and which also may be software-configurable. Upon receiving a memory access request including a memory address of a memory region, the memory controller identifies a software-configurable QoSID associated with the memory address, and associates the QoSID with a QoS policy state using the QoS policy table. The memory controller then applies the QoS policy state to perform the memory access operation.

公开(公告)号：US20180018268A1

公开(公告)日：2018-01-18

申请号：US15718449

申请日：2017-09-28

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Mark Anthony Rinaldi ,  Natarajan Vaidhyanathan

IPC: G06F12/04 ,  G06F12/12

CPC classification number: G06F12/0875 ,  G06F12/04 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/401

Abstract: Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some aspects, a compressed memory controller (CMC) provides an LLC comprising multiple LLC lines, each providing a plurality of sub-lines the same size as a system cache line. The contents of the system cache line(s) stored within a single LLC line are compressed and stored in system memory within the memory sub-line region corresponding to the LLC line. A master table stores information indicating how the compressed data for an LLC line is stored in system memory by storing an offset value and a length value for each sub-line within each LLC line. By compressing multiple system cache lines together and storing compressed data in a space normally allocated to multiple uncompressed system lines, the CMC enables compression sizes to be smaller than the memory read/write granularity of the system memory.

公开(公告)号：US20180018122A1

公开(公告)日：2018-01-18

申请号：US15718515

申请日：2017-09-28

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Natarajan Vaidhyanathan

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  H03M13/00 ,  H03M7/30 ,  G06F12/12

CPC classification number: G06F3/0638 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/0223 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/403 ,  G06F2212/466 ,  H03M7/30 ,  H03M13/6312 ,  Y02D10/13

Abstract: Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system is disclosed. In this regard, a compressed memory controller provides multiple CI hint directory entries, each providing a plurality of CI hints. The compressed memory controller receives a memory write request comprising write data, determines a compression pattern for the write data, and generates a CI for the write data based on the compression pattern. The compressed memory controller writes the write data to the memory line, and writes the generated CI into one or more ECC bits of the memory line. In parallel, the compressed memory controller determines whether the physical address corresponds to a CI hint directory entry, and, if so, a CI hint of the CI hint directory entry corresponding to the physical address is updated based on the generated CI.

公开(公告)号：US20170286308A1

公开(公告)日：2017-10-05

申请号：US15086817

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Colin Beaton Verrilli ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Mark Anthony Rinaldi ,  Natarajan Vaidhyanathan

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/04 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/401

Abstract: Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some aspects, a compressed memory controller (CMC) provides an LLC comprising multiple LLC lines, each providing a plurality of sub-lines the same size as a system cache line. The contents of the system cache line(s) stored within a single LLC line are compressed and stored in system memory within the memory sub-line region corresponding to the LLC line. A master table stores information indicating how the compressed data for an LLC line is stored in system memory by storing an offset value and a length value for each sub-line within each LLC line. By compressing multiple system cache lines together and storing compressed data in a space normally allocated to multiple uncompressed system lines, the CMC enables compression sizes to be smaller than the memory read/write granularity of the system memory.

公开(公告)号：US20170242793A1

公开(公告)日：2017-08-24

申请号：US15228320

申请日：2016-08-04

Applicant: QUALCOMM Incorporated

Inventor： Natarajan Vaidhyanathan ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Colin Beaton Verrilli

IPC: G06F12/0804

CPC classification number: G06F12/0804 ,  G06F12/0893 ,  G06F12/12 ,  G06F2212/1008 ,  G06F2212/281 ,  G11C2207/2245

Abstract: Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches is provided. In one aspect, a DRAM cache management circuit is provided to manage access to a DRAM cache in high-bandwidth memory. The DRAM cache management circuit comprises a DRAM cache indicator cache, which stores master table entries that are read from a master table in a system memory DRAM and that contain DRAM cache indicators. The DRAM cache indicators enable the DRAM cache management circuit to determine whether a memory line in the system memory DRAM is cached in the DRAM cache of high-bandwidth memory, and, if so, in which way of the DRAM cache the memory line is stored. Based on the DRAM cache indicator cache, the DRAM cache management circuit may determine whether to employ the DRAM cache and/or the system memory DRAM to perform a memory access operation in an optimal manner

公开(公告)号：US20170212840A1

公开(公告)日：2017-07-27

申请号：US15192019

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Hien Minh Le ,  Thuong Quang Truong ,  Natarajan Vaidhyanathan ,  Mattheus Cornelis Antonius Adrianus Heddes ,  Colin Beaton Verrilli

IPC: G06F12/08

CPC classification number: G06F12/0895 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1048 ,  G06F2212/305 ,  G06F2212/502

Abstract: Providing scalable dynamic random access memory (DRAM) cache management using tag directory caches is provided. In one aspect, a DRAM cache management circuit is provided to manage access to a DRAM cache in a high-bandwidth memory. The DRAM cache management circuit comprises a tag directory cache and a tag directory cache directory. The tag directory cache stores tags of frequently accessed cache lines in the DRAM cache, while the tag directory cache directory stores tags for the tag directory cache. The DRAM cache management circuit uses the tag directory cache and the tag directory cache directory to determine whether data associated with a memory address is cached in the DRAM cache of the high-bandwidth memory. Based on the tag directory cache and the tag directory cache directory, the DRAM cache management circuit may determine whether a memory operation can be performed using the DRAM cache and/or a system memory DRAM.