公开(公告)号：US09734878B1

公开(公告)日：2017-08-15

申请号：US15142316

申请日：2016-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Farrukh Aquil ,  Michael Drop ,  Vaishnav Srinivas ,  Philip Clovis

IPC: G11C7/10 ,  G11C11/408 ,  G11C11/407 ,  G11C11/4076 ,  G06F13/42 ,  G06F13/16

CPC classification number: G11C11/4093 ,  G06F13/1678 ,  G06F13/1694 ,  G06F13/4282 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.

公开(公告)号：US09246716B2

公开(公告)日：2016-01-26

申请号：US14663303

申请日：2015-03-19

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Sumeet Sethi ,  John Eaton ,  Vinodh Cuppu ,  Vikram Arora ,  Vaishnav Srinivas ,  Asim Muhammad Muneer ,  Isaac Berk

IPC: H03K19/003 ,  H04L25/02 ,  H03K19/0175 ,  G06F13/40 ,  H03K19/00

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  H03K19/0005 ,  H03K19/017545 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

公开(公告)号：US20150358001A1

公开(公告)日：2015-12-10

申请号：US14299779

申请日：2014-06-09

Applicant: QUALCOMM Incorporated

Inventor： Shraddha Sridhar ,  Vaishnav Srinivas

IPC: H03K3/017

CPC classification number: H03K3/017 ,  H03K5/1565

Abstract: A duty cycle correction circuit includes a rising edge variable delay circuit and a falling edge variable delay circuit. The variable delay for each delay circuit depends upon an uncorrected duty cycle for an uncorrected clock signal being corrected by the duty cycle correction circuit into a corrected clock signal having a desired duty cycle.

Abstract translation: 占空比校正电路包括上升沿可变延迟电路和下降沿可变延迟电路。 每个延迟电路的可变延迟取决于未被校正的时钟信号的未校正的占空比，其由占空比校正电路校正为具有期望占空比的校正时钟信号。

公开(公告)号：US20150294970A1

公开(公告)日：2015-10-15

申请号：US14252588

申请日：2014-04-14

Applicant: QUALCOMM Incorporated

Inventor： Renatas Jakushokas ,  Robert Won Chol Kim ,  Vaishnav Srinivas

IPC: H01L27/10 ,  H01L23/64 ,  H01L49/02

CPC classification number: H01L28/20 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/016 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Capacitor, resistor and resistor-capacitor components are described herein. In one embodiment, a die comprises first and second metal interconnect layers in a back end of line (BEOL) of the die, and an insulator between the first and second metal interconnect layers. The die also comprises a metal-insulator-metal (MIM) capacitor embedded in the insulator, the MIM capacitor comprising a first metal plate, a second metal plate, and a dielectric layer between the first and second metal plates. The die further comprises a metal resistor embedded in the insulator, wherein the metal resistor and the first metal plate of the MIM capacitor are formed from a same metal layer. In one example, the dielectric layer may have a higher dielectric constant than the insulator. In another example, the second metal plate of the MIM capacitor may overlap the metal resistor.

Abstract translation: 本文描述了电容器，电阻器和电阻器 - 电容器部件。 在一个实施例中，管芯包括管芯的后端（BEOL）中的第一和第二金属互连层以及第一和第二金属互连层之间的绝缘体。 模具还包括嵌入在绝缘体中的金属 - 绝缘体 - 金属（MIM）电容器，MIM电容器包括第一金属板，第二金属板和介于第一和第二金属板之间的电介质层。 模具还包括嵌入绝缘体中的金属电阻器，其中金属电阻器和MIM电容器的第一金属板由相同的金属层形成。 在一个示例中，电介质层可以具有比绝缘体更高的介电常数。 在另一示例中，MIM电容器的第二金属板可以与金属电阻器重叠。

公开(公告)号：US20150213849A1

公开(公告)日：2015-07-30

申请号：US14589145

申请日：2015-01-05

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  David Ian West

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G11C29/022 ,  G11C29/028

Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A training signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The training signal is then returned to the SoC, where it may be examined by a closed-loop training engine of the SoC. A training result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop training engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

Abstract translation: 提供使用端口到端口环回的动态随机存取存储器（DRAM）系统的存储器训练以及相关方法，系统和装置。 在一个方面，DRAM系统中的第一端口经由环回连接耦合到第二端口。 训练信号从片上系统（SoC）发送到第一个端口，并通过环回连接传递到第二个端口。 然后训练信号返回到SoC，在那里可以通过SoC的闭环训练引擎检查训练信号。 可以记录与硬件参数对应的训练结果，并且可以重复该过程，直到在闭环训练引擎上实现硬件参数的最佳结果。 通过使用端口到端口环回配置，关于与DRAM系统相关联的定时，功率和其他参数的DRAM系统参数可以被更快地训练并且具有较低的启动存储器使用。

公开(公告)号：US09088445B2

公开(公告)日：2015-07-21

申请号：US13787926

申请日：2013-03-07

Applicant: QUALCOMM Incorporated

Inventor： Dexter T. Chun ,  Sumeet S. Sethi ,  John D. Eaton ,  Vinodh R. Cuppu ,  Vikram Arora ,  Vaishnav Srinivas ,  Asim Muhammad Muneer ,  Isaac D. Berk

IPC: H03K17/16 ,  H04L25/02 ,  G06F13/40 ,  H03K19/00

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  H03K19/0005 ,  H03K19/017545 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

Abstract translation: 一种控制信号终止的方法包括：提供用于选择性地终止在双向数据总线上在第一设备处接收的信号的第一逻辑，提供用于选择性地终止在双向数据总线上的第二设备处接收的信号的第二逻辑，从第一设备发送第一信号 以第一速度传送到双向数据总线上的第二设备，在停止发送第一信号之后停止发送第一信号，使得第二逻辑能够使第二设备的参考电压从第一电平移位到 在第二设备启用第二逻辑之后，以更高的速度在双向数据总线上从第一设备向第二设备发送第二信号，并且基于在第一设备处接收到的信号的速度来控制第一逻辑 在双向数据总线上。

公开(公告)号：US20150194197A1

公开(公告)日：2015-07-09

申请号：US14591056

申请日：2015-01-07

Applicant: QUALCOMM Incorporated

Inventor： David Ian West ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  Vaishnav Srinivas

IPC: G11C7/10

CPC classification number: G11C7/1063 ,  G06F11/1004 ,  G06F11/1048 ,  G06F12/00 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

Abstract translation: 公开了动态随机存取存储器（DRAM）反向通道通信系统和方法。 在一个方面，反向通道通信系统允许DRAM将错误校正信息传送到片上系统（SoC），应用处理器（AP）或其他存储器控制器上来刷新警报信息。

公开(公告)号：US20140367757A1

公开(公告)日：2014-12-18

申请号：US13917549

申请日：2013-06-13

Applicant: QUALCOMM Incorporated

Inventor： Renatas Jakushokas ,  Vaishnav Srinivas ,  Robert Won Chol Kim

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01G4/002 ,  H01G4/005 ,  H01G4/33 ,  H01G4/385 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a low-voltage capacitor and a high-voltage capacitor. The low-voltage capacitor comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, a third electrode formed from a third metal layer, a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third electrodes. The high-voltage capacitor comprises a fourth electrode formed from the first metal layer, a fifth electrode formed from the third metal layer, and a third dielectric layer between the fourth and fifth electrodes, wherein the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.

Abstract translation: 本文描述了能够提供低电压电容器和高压电容器的电容器结构。 在一个实施例中，电容器结构包括低压电容器和高压电容器。 低电压电容器包括由第一金属层形成的第一电极，由第二金属层形成的第二电极，由第三金属层形成的第三电极，第一和第二电极之间的第一介电层，以及第二电极 电介质层在第二和第三电极之间。 高压电容器包括由第一金属层形成的第四电极，由第三金属层形成的第五电极和在第四和第五电极之间的第三电介质层，其中第三电介质层比第一电介质层厚 层或第二电介质层。